EZ80L925048MOD Datasheet, PDF (20/38 Pages) Zilog, Inc. – eZ80L92 Module is a compact, high-performance Ethernet module

eZ80L925048MOD
eZ80L92 Module Product Specification
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the module is required for this function. In this case, the PD6 pin is not available
for GPIO on the I/O connector.
EMAC Ports
Chip Select CS3 is used for selecting the EMAC via I/O decoding. The I/O base
address is user-selectable. The EMAC is connected as an 8- or 16-bit device with
8-word-wide I/O registers:
EMAC Wait States
The CS8900A EMAC should be operated in Intel bus mode so that the setup and
hold times for the I/O access are met. For 48 MHz operation, first set CS3_BMC (I/
O address 0xF3h) to 84h (Intel bus mode with four system clock cycles per bus
cycle) and then CS3_CTL (I/O Address 0xB3) to 18h (0 wait states for I/O). For a
20.8 ns CPU Clock cycle time, the Read and Write access time is:
2 x 4 x 20.8 ns–16 ns (for capacitive and chip delays) = 150 ns
Memory
The eZ80L92 Module offers SRAM and Flash memories and the wait states that
support memory operations, as described in this section.
Wait States
To ensure that valid data is read from or written to slower memories, a number of
wait states must be inserted into the memory or I/O access operations by the pro-
cessor. The number of wait states that are required should be added by program-
ming the chip select control registers. To calculate the minimum number of wait
states required, refer to Table 4.
Table 4. Chip Frequency to Wait State Cycle Time Calculation
MHz
12
20
24
36
40
48
Cycle Time
83.3 ns
50.0 ns
41.7 ns
27.8 ns
25.0 ns
20.8 ns
PS017005-0903
PRELIMINARY
Onboard Component Description