EZ80L925048MOD Datasheet, PDF (17/38 Pages) Zilog, Inc. – eZ80L92 Module is a compact, high-performance Ethernet module

eZ80L925048MOD
eZ80L92 Module Product Specification
11
Table 2. eZ80L92 Module I/O Connector Pin Identification* (Continued)
Pin # Symbol
Pull
Signal
Up/Down Direction
Comments
46 GND
47 HALT_SLP
V_SS/Ground (0 V).
Output, Active A Low on this pin indicates that the eZ80^® CPU
Low
enters either HALT or SLEEP mode because of exe-
cution of either a HALT or SLP instruction.
48 NMI
PU 10KΩ Schmitt Trig-
ger Input,
Active Low
The NMI input is a higher priority input than the
maskable interrupts. It is always recognized at the
end of an instruction, regardless of the state of the
interrupt enable control bits. This input includes a
Schmitt trigger to allow RC rise times. This external
NMI signal is combined with an internal NMI signal
generated from the WDT block before being con-
nected to the NMI input of the eZ80^® CPU.
49
V_DD
50 Reserved
3.3 V supply input pin.
NC
Reserved—No Connection.
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either V_DD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS017005-0903
PRELIMINARY
Pin Description