EZ80L925048MOD Datasheet, PDF (16/38 Pages) Zilog, Inc. – eZ80L92 Module is a compact, high-performance Ethernet module

eZ80L925048MOD
eZ80L92 Module Product Specification
10
Table 2. eZ80L92 Module I/O Connector Pin Identification* (Continued)
Pin # Symbol
Pull
Signal
Up/Down Direction
Comments
27 TDO
Output
JTAG data output pin.
28
TDI/ZDA
PU 10KΩ Input
JTAG data input pin.
29 GND
30 TRIGOUT
Output
V_SS/Ground (0 V).
Active High trigger event indicator.
31 TCK/ZCL PU 10KΩ Input
JTAG clock. High on reset enables ZDI mode; Low
on reset enables OCI debug.
32 TMS
PU 10KΩ Input
JTAG Test Mode Select.
33
RTC_V_DD
RTC supply from GoldCap (or external battery).
34 EZ80CLK
Output
48 MHz synchronous CPU clock.
35 SCL
PU 4k7 Bidirectional I²C Bus Clock.
36 GND
37 SDA
PU 4k7
Bidirectional
V_SS/Ground (0 V).
I²C Bus Data.
38 GND
39 FlashWE PU 10KΩ Input
V_SS/Ground (0 V).
Low enables Write to onboard Flash memory. If this
pin is unconnected, the Flash memory is write-
protected.
40 GND
41 CS3
Output
V_SS/Ground (0 V).
Used on module for CS8900 EMAC.
42 DIS_IRDA PU 10KΩ Input
Low disables onboard IRDA transceiver to use PD0/
PD1 UART pins externally.
43 RESET
44 WAIT
PU 2k2
PU 2k2
Bidirectional
Input
Reset output from Module or push-button reset.
Driving the WAIT pin Low forces the eZ80^® CPU to
provide additional clock cycles for an external
peripheral or external memory to complete its Read
or Write operation.
45
V_DD
3.3 V supply input pin.
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either V_DD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS017005-0903
PRELIMINARY
Pin Description