EZ80L925048MOD Datasheet, PDF(14/38 Page) Zilog, Inc. – eZ80L92 Module is a compact, high-performance Ethernet module

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EZ80L925048MOD Datasheet, PDF (14/38 Pages) Zilog, Inc. – eZ80L92 Module is a compact, high-performance Ethernet module

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eZ80L925048MOD

eZ80L92 Module Product Specification

I/O Connector

Figure 3 illustrates the pin layout of the 50-pin I/O Connector, located at position

JP2 of the eZ80L92 Module. Table 2 describes the pins and their functions.

PB7

PB5

PB3

PB1

GND_EXT

PC6

PC4

PC2

PC0

PD6

PD5

PD3

PD1

TDO

GND_EXT

TCK

RTC_VDD

IICSCL

IICSDA

FLASHWE

CS3

RESET

V3.3_EXT

HALT_SLP

V3.3_EXT

JP2

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

41 42

43 44

45 46

47 48

49 50

HEADER 25X2

IDC50

PB6

PB4

PB2

PB0

PC7

PC5

PC3

PC1

PD7

GND_EXT

PD4

PD2

PD0

TDI

TRIGOUT

TMS

EZ80CLK

GND_EXT

DIS_IRDA

WAIT

GND_EXT

NMI

Figure 3. eZ80L92 Module I/O Connector Pin Configuration

Table 2. eZ80L92 Module I/O Connector Pin Identification*

Pin # Symbol

Pull

Signal

Up/Down Direction

Comments

PB7

Bidirectional

PB6

Bidirectional

Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0âD7 and A0âA23 should be below 10 pF to satisfy

timing requirements for the CPU.

All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power

consumption and to reduce noise sensitivity.

To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down

All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.

PS017005-0903

PRELIMINARY

Pin Description

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