EZ80L925048MOD Datasheet, PDF (13/38 Pages) Zilog, Inc. – eZ80L92 Module is a compact, high-performance Ethernet module

eZ80L925048MOD
eZ80L92 Module Product Specification
7
Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification* (Continued)
Pin # Symbol
Pull
Up/Down* Signal Direction Comments
44 IORQ
Bidirectional
45 GND
46 RD
Bidirectional
V_SS/Ground (0 V).
47 WR
Bidirectional
48 INSTRD
Output
49 BUSACK
PU 10KΩ Output
50 BUSREQ
PU 10KΩ Input
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the eZ80^® CPU.
All unused inputs should be pulled to either V_DD or GND, depending on their inactive levels to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS017005-0903
PRELIMINARY
Pin Description