Z16C32SL Datasheet, PDF (16/22 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

Z16C32 SL1660 ONLY
IUSC^™ Integrated Universal Serial Controller
Zilog
No Symbol
Parameter
V_CC
T_A = 0°C to +70°C
Min
Max
Units Note(s)
151 TsAD(AS)
Address to /AS Rise Setup Time
10
152 ThAD(AS)
Address to /AS Rise Hold Time
10
153 TsW(CLK)
/WAIT to CLK Fall Setup Time
10
154 ThW(CLK)
/WAIT to CLK Fall Hold Time
15
ns
6
ns
6
ns
6
ns
6
155 TsRDY(CLK)
/READY to CLK Fall Setup Time
10
ns
6
156 ThRDY(CLK)
/READY to CLK Fall Hold Time
15
157 ThDW(CLK)
Write Data to CLK Rise Hold Time
0
158 TdAS(DSw)
/AS Rise to /DS Fall (Write) Delay
40
159 TsDW(DS)
Write Data to /DS Fall Setup Time
20
160 TwDSlw
/DS (Write) Low Width
45
161 ThDW(DS)
Write Data to /DS Rise Hold Time
20
162 TdAS(WR)
/AS Rise to /WR Fall Delay
40
ns
6
ns
6
ns
6,10
ns
6, 7
ns
6, 11
ns
6, 8
ns
6, 10
163 TsDW(WR)
Write Data to /WR Fall Setup Time
20
ns
6, 7
164 TwWRl
165 ThDW(WR)
166 TdCLK(WR)
167 TdCLK(BUSz)
168 TsABT(CLK)
169 ThABT(CLK)
170 TdCLK(BRQ)
/WR Low Width
Write Data to /WR Rise Hold Time
CLK Fall to /WR Delay
CLK Rise to Bus Float Delay
/ABORT to CLK Rise Setup Time
/ABORT to CLK Rise Hold Time
CLK Rise to /BUSREQ Delay
45
ns
6, 11
20
ns
6, 8
25
ns
6
25
ns
6
20
ns
6
15
ns
6
25
ns
6
171 TdCLK(BUSa) CLK Rise to Bus Active Delay
25
ns
6
172 TsBIN(CLK)
173 ThBIN(CLK)
174 TsBRQ(CLK)
175 ThBRQ(CLK)
176 TdBIN(BOT)
/BIN to CLK Rise Setup Time
/BIN to CLK Rise Hold Time
/BUSREQ to CLK Rise Setup Time
/BUSREQ to CLK Rise Hold Time
/BIN to /BOUT Delay
20
ns
6
15
ns
6
25
ns
6
0
ns
6
60
ns
Notes:
AC Test Conditions:
V_CC = 5V ±10% unless otherwise specified, over specified temperature range.
V_IH = 2.0V VOH = 2.0V
V_IL = 0.8V VOL = 0.8V
Float = +0.5V
1. Direct Address is any of S//D, D//C or AD15-AD8 used as an address bus.
2. The parameter applies only when /AS is not present.
3. Strobe is any of /DS, /RD, /WR or Pulsed /INTACK.
4. Parameter applies only if read empties the receive FIFO.
5. Parameter applies only if write fills the transmit FIFO.
6. Parameter applies only while the IUSC is bus master.
7. Parameter is clock-cycle dependent, TwCLKh + TfCLK - 5.
8. Parameter is clock-cycle dependent, TwCLKl + TrCLK - 5.
9. Parameter is clock-cycle dependent, TcCLK + TwCLKh + TfCLK - 5.
10. Parameter is clock-cycle dependent, TcCLK - 10.
11. Parameter is clock-cycle dependent, TcCLK -5.
Values shown for parameters with notes 7, 8, 9, 10, or 11 are calculated using corresponding equations with minimum values.
1-16
PRELIMINARY
CP97HHS0100