Z16C32SL Datasheet, PDF (14/22 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

Z16C32 SL1660 ONLY
IUSC^™ Integrated Universal Serial Controller
No Symbol
45 TdWRr(TRQ)
46 TsCS(DS)
47 ThCS(DS)
48 TsADD(DS)
49 ThADD(DS)
50 TsSIA(DS)
51 ThSIA(DS)
52 TsCS(RD)
53 ThCS(RD)
54 TsADD(RD)
55 ThADD(RD)
56 TsSIA(RD)
57 ThSIA(RD)
58 TsCS(WR)
59 ThCS(WR)
60 TsADD(WR)
61 ThADD(WR)
62 TsSIA(WR)
63 ThSIA(WR)
78 TdDSf(RDY)
79 TdRDY(DRv)
80 TdDSr(RDY)
81 TsIEI(DSI)
82 ThIEI(DSI)
83 TdIEI(IEO)
84 TdAS(IEO)
85 TdDSI(INT)
86 TdDSI(Wf)
87 TdDSI(Wr)
88 TdW(DRv)
89 TdRDf(RDY)
90 TdRDr(RDY)
91 TsIEI(RDI)
92 ThIEI(RDI)
93 TdRDI(INT)
94 TdRDI(Wf)
95 TdRDI(Wr)
96 TwPIAl
97 TwPIAh
98 TdAS(PIA)
99 TdPIA(AS)
100 TdPIA(DRa)
101 TdPIA(DRn)
102 TdPIA(DRz)
103 TsIEI(PIA)
104 ThIEI(PIA)
V_CC
Parameter
Min
/WR Rise to /TxREQ Active Delay
0
/CS to /DS Fall Setup Time
0
/CS to /DS Fall Hold Time
25
Direct Address to /DS Fall Setup Time
5
Direct Address to /DS Fall Hold Time
25
Status /INTACK to /DS Fall Setup time
5
Status /INTACK to /DS Fall Hold Time
25
/CS to /RD Fall Setup Time
0
/CS to /RD Fall Hold Time
25
Direct Address to /RD Fall Setup Time
5
Direct Address to /RD Fall Hold Time
25
Status /INTACK to /RD Fall Setup Time
5
Status /INTACK to /RD Fall Hold Time
25
/CS to /WR Fall Setup Time
0
/CS to /WR Fall Hold Time
25
Direct Address to /WR Fall Setup Time
5
Direct Address to /WR Fall Hold Time
25
Status /INTACK to /WR Fall Setup Time
5
Status /INTACK to /WR Fall Hold Time
25
/DS Fall (Intack) to /RDY Fall Delay
/RDY Fall to Data Valid Delay
/DS Rise to /RDY Rise Delay
IEI to /DS Fall (Intack) Setup Time
10
IEI to /DS Rise (Intack) Hold Time
0
IEI to IEO Delay
/AS Rise (Intack) to IEO Delay
/DS Fall to /INT Inactive Delay
/DS Fall (Intack) to /WAIT Fall Delay
/DS Fall (Intack) to /WAIT Rise Delay
/WAIT Rise to Data Valid Delay
/RD Fall (Intack) to /RDY Fall Delay
/RD Rise to /RDY Rise Delay
IEI to /RD Fall (Intack) Setup Time
10
IEI to /RD Rise (Intack) Hold Time
0
/RD Fall (Intack) to /INT Inactive Delay
/RD Fall (Intack) to /WAIT Fall Delay
/RD Fall (Intack) to /WAIT Rise Delay
Pulsed /INTACK Low Width
60
Pulsed /INTACK High Width
50
/AS Rise to Pulsed /INTACK Fall Delay Time
5
Pulsed /INTACK Rise to /AS Fall Delay Time
5
Pulsed /INTACK Fall to Data Active Delay
0
Pulsed /INTACK Rise to Data Not Valid Delay
0
Pulsed /INTACK Rise to Data Float Delay
IEI to Pulsed /INTACK Fall Setup Time
10
IEI to Pulsed /INTACK Rise Hold Time
0
Zilog
T_A = 0°C to +70°C
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
ns
40
ns
40
ns
ns
ns
30
ns
60
ns
200
ns
40
ns
200
ns
40
ns
200
ns
40
ns
ns
ns
200
ns
40
ns
200
ns
ns
ns
ns
ns
ns
ns
20
ns
ns
ns
Note(s)
2
2
1,2
1,2
2
2
2
2
1,2
1,2
2
2
2
2
1,2
1,2
2
2
1-14
PRELIMINARY
CP97HHS0100