Z16C32SL Datasheet, PDF (15/22 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

Zilog
No Symbol
105 TdPIA(IEO)
106 TdPIA(INT)
107 TdPIAf(RDY)
108 TdPIAr(RDY)
109 TdPIA(Wf)
110 TdPIA(Wr)
111 TdSIA(INT)
112 TwSTBh
113 TwRESl
114 TwRESh
115 TdRES(STB)
116 TdDSf(RDY)
117 TdWRf(RDY)
118 TdWRr(RDY)
119 TdRDf(RDY)
120 TwCLKl
121 TwCLKh
122 TcCLK
123 TfCLK
124 TrCLK
125 TdCLKr (UAS)
126 TwUASl
127 TdCLKf(UAS)
128 TdCLKr(AS)
129 TwASl
130 TdCLKf(AS)
131 TdAS(DSr)
132 TdCLKr(DS)
133 TwDSlr
134 TdCLKf(DS)
135 TsDR(DS)
136 ThDR(DS)
137 TdCLK(RW)
138 TdAS(RD)
139 TdCLKr(RD)
140 TwRDl
141 TdCLKf(RD)
142 TsDR(RD)
143 ThDR(RD)
144 TdCLK(ADD)
145 TdCLK(AD)
146 ThAD(PC)
147 TdCLK(ADz)
148 TdCLK(ADa)
149 TsAD(UAS)
150 ThAD(UAS)
Z16C32 SL1660 ONLY
IUSC^™ Integrated Universal Serial Controller
V_CC
T_A = 0°C to +70°C
Parameter
Pulsed /INTACK Fall to IEO Delay
Min
Max
Units Note(s)
60
ns
1
Pulsed /INTACK Fall to /INT Inactive Delay
200
ns
Pulsed /INTACK Fall to /RDY Fall Delay
200
ns
Pulsed /INTACK Rise to /RDY Rise Delay
40
ns
Pulsed /INTACK Fall to /WAIT Fall Delay
40
ns
Pulsed /INTACK Fall to /WAIT Rise Delay
200
ns
Status /INTACK Fall to IEO Inactive Delay
200
ns
2
/Strobe High Width
50
ns
3
/RESET Low Width
170
ns
/RESET High Width
60
ns
/RESET Rise to /STB Fall
60
ns
3
/DS Fall to /RDY Fall Delay
50
ns
/WR Fall to /RDY Fall Delay
50
ns
/WR Rise to /RDY Rise Delay
40
ns
/RD Fall to /RDY Fall Delay
50
ns
CLK Low Width
25
ns
CLK High Width
25
ns
CLK Cycle Time
50
ns
CLK Fall Time
5
ns
CLK Rise Time
5
ns
CLK Rise to /UAS Fall Delay
25
ns
6
/UAS Low Width
20
ns
6,7
CLK Fall to /UAS Rise Delay
25
ns
6
CLK Rise to /AS Fall Delay
25
ns
6
/AS Low Width
20
ns
6,7
CLK Fall to /AS Rise Delay
25
ns
6
/AS Rise to /DS Fall (Read) Delay
20
ns
6,8
CLK Rise to /DS Delay
25
ns
6
/DS (Read) Low Width
70
ns
6,9
CLK Fall to /DS Delay
25
ns
6
Read Data to /DS Rise Setup Time
30
ns
6
Read Data to /DS Rise Hold Time
0
ns
6
CLK Rise to R//W Delay
25
ns
6
/AS Rise to /RD Fall Delay
20
ns
6,8
CLK Rise to /RD Delay
25
ns
6
/RD Low Width
70
ns
6,9
CLK Fall to /RD Delay
25
ns
6
Read Data to /RD Rise Setup Time
30
ns
6
Read Data to /RD Rise Hold Time
0
ns
6
CLK Rise to Direct Address Delay
25
ns
1,6
CLK Rise to Address Delay
TdCLKf(DS) 25
ns
6
Address to CLK Rise Hold Time
0
ns
6
CLK Rise to Address Float Delay
25
ns
6
CLK Rise to Address Active Delay
25
ns
6
Address to /UAS Rise Setup Time
10
ns
6
Address to /UAS Rise Hold Time
10
ns
6
CP97HHS0100
PRELIMINARY
1-15