ZL50015 Datasheet, PDF (97/122 Pages) Zarlink Semiconductor Inc – Enhanced 1 K Digital Switch with Stratum 4E DPLL

ZL50015
Data Sheet
AC Electrical Characteristics^† - Intel Non-Multiplexed Bus Mode - Write Access
Characteristics
Sym. Min. Typ. Max. Units
Test Conditions²
1 CS de-asserted time
2 WR setup to CS falling
3 RD setup to CS falling
4 Address setup to CS falling
5 Data setup to CS falling
6 WR hold after CS rising
7 RD hold after CS rising
8 Address hold after CS rising
9 Data hold after CS rising
t_CSD
15
t_WS
10
t_RS
10
t_AS
5
t_DS
0
t_WH
0
t_RH
0
t_AH
10
t_DH
5
ns
ns
ns
ns
ns C_L = 50 pF
ns
ns
ns
ns C_L = 50 pF, R_L = 1 K
(Note 1)
10 Acknowledgement delay time.
t_AKD
From CS low to RDY high:
Registers
Memory
55
150
ns
ns
C_L = 50 pF
C_L = 50 pF
11 Acknowledgement hold time.
From CS high to RDY low
t_AKH
4
12
ns C_L = 50 pF, R_L = 1 K
(Note 1)
12 RDY drive low to HiZ
t_AKZ
8
ns
Note 1:
Note 2:
High impedance is measured by pulling to the appropriate rail with R_L, with timing corrected to cancel time taken to
discharge C_L.
A delay of 500 µs to 2 ms (Section 17.2 on page 46) must be applied before the first microprocessor access is performed
after the RESET pin is set high.
† Characteristics are over recommended operating conditions unless otherwise stated.
CS
WR
RD
A0-A13
D0-D15
RDY
t_CSD
t_WS
t_WH
t_RS
t_RH
t_AS
t_AH
VALID ADDRESS
t_DS
t_DH
VALID WRITE DATA
t_AKZ
t_AKD
t_AKH
Figure 29 - Intel Non-Multiplexed Bus Timing - Write Access
V_CT
V_CT
V_CT
V_CT
V_CT
V_CT
97
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