ZL50015 Datasheet, PDF (86/122 Pages) Zarlink Semiconductor Inc – Enhanced 1 K Digital Switch with Stratum 4E DPLL

ZL50015
Data Sheet
24.0 Memory
24.1 Memory Address Mappings
When A13 is high, the data or connection memory can be accessed by the microprocessor port. Bit 1 - 0 in the
Control Register determine the access to the data or connection memory (CM_L or CM_H).
MSB
(Note 1)
Stream Address
(St0 - 15)
Channel Address
(Ch0 - 255)
A13
A12 A11 A10 A9 A8 Stream [n] A7 A6 A5 A4 A3 A2 A1 A0
Channel [n]
1
0
0
0
0
0
Stream 0
0 0 0 0 0 0 0 0 Ch 0
1
0
0
0
0
1
Stream 1
0 0 0 0 0 0 0 1 Ch 1
1
0
0
0
1
0
Stream 2
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1
0
0
0
1
1
Stream 3
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1
0
0
1
0
0
Stream 4
0 0 0 1 1 1 1 0 Ch 30
1
0
0
1
0
1
Stream 5
0 0 0 1 1 1 1 1 Ch 31 (Note 2)
1
0
0
1
1
0
Stream 6
0 0 1 0 0 0 0 0 Ch 32
1
0
0
1
1
1
Stream 7
0 0 1 0 0 0 0 1 Ch 33
1
0
1
0
0
0
Stream 8
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0 0 1 1 1 1 1 0 Ch 62
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0 0 1 1 1 1 1 1 Ch 63 (Note 3)
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1
0
1
1
1
0
Stream 14
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1
0
1
1
1
1
Stream 15
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0 1 1 1 1 1 1 0 Ch126
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0 1 1 1 1 1 1 1 Ch 127 (Note 4)
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1 1 1 1 1 1 1 0 Ch 254
1 1 1 1 1 1 1 1 Ch 255 (Note 5)
Notes:
1. A13 must be high for access to data and connection memory positions. A13 must be low to access internal registers.
2. Channels 0 to 31 are used when serial stream is at 2.048 Mbps.
3. Channels 0 to 63 are used when serial stream is at 4.096 Mbps.
4. Channels 0 to 127 are used when serial stream is at 8.192 Mbps.
5. Channels 0 to 255 are used when serial stream is at 16.384 Mbps.
Table 50 - Address Map for Memory Locations (A13 = 1)
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Zarlink Semiconductor Inc.