ZL50015 Datasheet, PDF (66/122 Pages) Zarlink Semiconductor Inc – Enhanced 1 K Digital Switch with Stratum 4E DPLL

ZL50015
Data Sheet
External Read/Write Address: 0042_H
Reset Value: 16B1_H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CFN
15
CFN
14
CFN
13
CFN
12
CFN
11
CFN
10
CFN
9
CFN
8
CFN
7
CFN
6
CFN
5
CFN
4
CFN
3
CFN
2
CFN
1
CFN
0
Bit
Name
Description
15 - 0
CFN15 - 0 Center Frequency Number (CFN) Lower 16 Bits: The total binary value of these bits
and the CFRU register bits defines the output center frequency number according to the
following formula:
fOUT = ^{C-----F----N--} × fMCLK
2²⁶
where, f_OUT is desired output center frequency, while f_MCLK is frequency of DPLL master
clock. For given master clock frequency of 100 MHz, and desired output center fre-
quency of 65.536 MHz, the CFN has the value of:
CFN
=
2²⁶
×
6----5---.--5---3----6---M------H----z--
100MHz
=
2²⁶ × 0.65536
=
43980465
=
29F16B1H
The register contents should be changed only if compensation for input oscillator (or
crystal) frequency offset is required.
e.g., if master clock frequency is off by +20 ppm (100.002 MHz -> 5 times multiplied c20i
of 20.0004 MHz), the CFN should be programmed to be:
CFN
=
2²⁶
×
--6---5----.--5---3---6----M-----H-----z---
100.002MHz
=
2²⁶ × 0.65534689
=
43979585
=
29F1341H
The default value of this register SHOULD NOT be changed in any other circumstances.
Table 28 - Centre Frequency Register - Lower 16 Bits (CFRL)
External Read/Write Address: 0043_H
Reset Value: 029F_H
15
14
13
12
11
0
0
0
0
0
10
9
8
7
6
5
4
3
2
1
0
0
CFN CFN CFN CFN CFN CFN CFN CFN CFN CFN
25
24
23
22
21
20
19
18
17
16
Bit
Name
Description
15 - 10 Unused Reserved. In normal functional mode, these bits MUST be set to zero.
9-0
CFN25 - 16
Center Frequency Number (CFN) Upper 10 Bits: The total binary value of these bits
and the CFRL register bits represents the center frequency number (CFN) explained
under CFRL register bits explanation.
The default value of this register should be changed only if compensation for input oscil-
lator (or crystal) frequency offset is required, and SHOULD NOT be changed in any other
circumstances.
Table 29 - Centre Frequency Register - Upper 10 Bits (CFRU)
66
Zarlink Semiconductor Inc.