ZL50015 Datasheet, PDF (69/122 Pages) Zarlink Semiconductor Inc – Enhanced 1 K Digital Switch with Stratum 4E DPLL

ZL50015
Data Sheet
External Read/Write Address: 0049_H
Reset Value: 099F_H (see Note)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
SRL SRL SRL SRL SRL SRL SRL SRL SRL SRL SRL SRL SRL
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Name
Description
15 - 13 Unused Reserved
In normal functional mode, these bits MUST be set to zero.
12 - 0
SRL12 - 0
Slew Rate Limit Bits
The binary value of these bits defines the maximum rate of DPLL phase change (phase
slope), where the phase represents difference between the input reference and output
feedback clock. Defined in same units as CFN (unsigned).
Note: The default value is ±56 ppm (’h099F/CFN = 56 ppm).
Table 33 - Slew Rate Limit Register (SRLR) Bits
External Read/Write Address: 004B_H
Reset Value: 0000_H
15
14
13
12
11
10
9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
MTR PRS PRS PMS PMS PMS FDM FDM
1
0
2
1
0
1
0
Bit
15 - 8
7
Name
Unused
MTR
Description
Reserved
In normal functional mode, these bits MUST be set to zero.
MTIE Reset
When this bit is low, the MTIE circuit applies a phase offset between the reference input
clock and the DPLL output clock and the phase offset value is maintained. When this bit
is high, MTIE circuit is in its reset state and the phase offset value is reset to zero,
causing alignment of the DPLL output clocks to nearest edge of the selected input
reference.
Table 34 - Reference Change Control Register (RCCR) Bits
69
Zarlink Semiconductor Inc.