ZL50409 Datasheet, PDF (69/135 Pages) Zarlink Semiconductor Inc – Managed 9-Port 10/100M Ethernet Switch

ZL50409
Data Sheet
12.2.3 DATA_FRAME_REG
• Data of indirectly accessed registers (8 bits)
• Address = 2 (read/write)
12.2.4 CONTROL_FRAME_REG
• CPU transmit/receive switch frames (8/16 bits)
• Address = 3 (read/write)
• Format:
8-byte of Frame status (Frame size, Source port #, VLAN tag)
Frame Data (size should be in multiple of 8-byte)
12.2.5 COMMAND&STATUS Register
• CPU interface commands and status (8 bits)
• Address = 4 (read/write)
• When the CPU writes to this register
Bit [0]:
Set Control Frame Receive buffer ready, after CPU writes a complete frame into the buffer. This bit
is self-cleared.
Bit [1]:
Set Control Frame Transmit buffer1 ready, after CPU reads out a complete frame from the buffer.
This bit is self-cleared.
Bit [2]:
Set Control Frame Transmit buffer2 ready, after CPU reads out a complete frame from the buffer.
This bit is self-cleared.
Bit [3]:
Set this bit to indicate CPU received a whole frame (transmit FIFO frame receive done), and
flushed the rest of frame fragment, If occurs. This bit will be self-cleared.
Bit [4]:
Set this bit to indicate that the following Write to the Receive FIFO is the last one (EOF). This bit
will be self-cleared.
Bit [5]:
Set this bit to re-start the data that is sent from the CPU to Receive FIFO (re-align). This feature
can be used for software debug. For normal operation must be '0'.
Bits [7:6]: Reserved. Must be '0'
• When the CPU reads this register:
Bit [0]:
Control Frame receive buffer ready, CPU can write a new frame
1 – CPU can write a new control command 1
0 – CPU has to wait until this bit is 1 to write a new control command 1
Bit [1]:
Control Frame transmit buffer1 ready for CPU to read
1 – CPU can read a new control command 1
0 – CPU has to wait until this bit is 1 to read a new control command
Bit [2]:
Control Frame transmit buffer2 ready for CPU to read
1 – CPU can read a new control command 1
0 – CPU has to wait until this bit is 1 to read a new control command
Bit [3]:
Transmit FIFO has data for CPU to read (TXFIFO_RDY)
Bit [4]:
Receive FIFO has space for incoming CPU frame (RXFIFO_SPOK)
Bit [5]:
Bits [7:6]:
Transmit FIFO End Of Frame (TXFIFO_EOF)
Reserved
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