ZL50409 Datasheet, PDF (105/135 Pages) Zarlink Semiconductor Inc – Managed 9-Port 10/100M Ethernet Switch

ZL50409
Data Sheet
The checksum formula is:
FF
Σ I²C register = 0
i=0
When the ZL50409 boots from the EEPROM the checksum is calculated and the value must be zero. If the
checksum is not zeroed the ZL50409 does not start and pin CHECKSUM_OK is set to zero.
12.3.7.13 LHBTimer – Link Heart Beat Timeout Timer
CPU Address:h610
Accessed by CPU (R/W)
In slot time (512 bit time). LHB packet will be sent out to the remote device if no other packet is transmitted in half
this period. The receiver will trigger LHB timeout interrupt if not receiving any good packet in this period.
12.3.7.14 LHBReg0, LHBReg1 - Link Heart Beat OpCode
CPU Address:h611, h612
Accessed by CPU (R/W)
The LHB frame uses MAC control frame format (same as flow control frame.) The register here defines the
operation code (we recommend h00-12).
12.3.7.15 fMACCReg0, fMACCReg1 - MAC Control Frame OpCode
CPU Address:h613, h614
Accessed by CPU (R/W)
The registers define the operation code if MAC control frame is forced out by processor.
12.3.7.16 FCB Base Address Register 0
I²C Address 0BF, CPU Address:h620
Accessed by CPU and I²C (R/W)
Bits [7:0]
FCB Base address bit 7:0 (Default 0)
12.3.7.17 FCB Base Address Register 1
I²C Address 0C0, CPU Address:h621
Accessed by CPU and I²C (R/W)
Bits [7:0]
FCB Base address bit 15:8 (Default 0x60)
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