ZL50409 Datasheet, PDF (125/135 Pages) Zarlink Semiconductor Inc – Managed 9-Port 10/100M Ethernet Switch

ZL50409
13.4.3 Typical CPU Timing Diagram for a CPU Read Cycle
Data Sheet
P_A[2:0]
P_CS#
P_RD#
P_D ATA
(t oC PU )
ADDR0
T_RH
T_RS
ADDR1
T _RS
T_RH
T_RA
Activ eTim e
T_RR
R ecov ery Tim e
T_RA
Activ eTim e
T_DI
T_DV
D ATA0
T_DI
T_DV
D ATA1
Valid tim e
Inv alidtim e
Figure 15 - Typical CPU Timing Diagram for a CPU Read Cycle
Description
(SCLK=100 Mhz) (SCLK=50 Mhz)
Refer to Figure 15
Read Cycle
Read Set up Time
Read Active Time
Read Hold Time
Read Recovery time
Data Valid time
Data Invalid time
Symbol
Min. Max. Min. Max.
T_RS
10
10
P_A and P_CS# to falling
edge of P_RD#
T_RA
20
T_RH
2
40
At least 2 SCLK cycles
2
P_A and P_CS# to rising
edge of P_RD#
T_RR
30
60
At least 3 SCLK cycles
T_DV
12
12 P_DATA to falling edge of
P_RD#
T_DI
10
10 P_DATA to rising edge of
P_RD#
Table 14 - AC Characteristics - CPU Read Cycle
125
Zarlink Semiconductor Inc.