ZL50409 Datasheet, PDF (14/135 Pages) Zarlink Semiconductor Inc – Managed 9-Port 10/100M Ethernet Switch

ZL50409
Ball Signal Description Table (continued)
Ball No(s)
Symbol
Test Interface
C11, C10, D10, C9,
C8, D8, C7, D7, C6,
C5, C4, D4, C3, D3,
C2, D2
TSTOUT[15:0]
I/O
Output
Test Facility
C13
C12
B13
B14
D11
D6
TDI
TRST#
TCK
TMS
TDO
SCAN_EN
Input
with pull-up
Input
with pull-up
Input
with pull-up
Input
with pull-up
Output
Input
Must be externally
pulled-down
System Clock, Power, and Ground Pins
A1
SCLK
Input
D9, H4, H13, N7,
V_DD
D5, D12, E4, E13, M4, V_CC
M13, N5,
G7-10, H7-10, J7-10, V_SS
K7-10
Misc.
D1
RESIN#
C1
RESETOUT#
F1
M_MDC
F2
M_MDIO
Power
Power
Power Ground
Input
Output
Output
I/O-TS
with pull-up
Data Sheet
Description
[15:4] Reserved
[3] EEPROM checksum is good
[2] Initialization Completed
[1] Memory Self Test in progress
[0] Initialization started
These pins also serve as bootstrap pins.
JTAG - Test Data In
JTAG - Test Reset
JTAG - Test Clock
JTAG - Test Mode State
JTAG - Test Data Out
Scan Enable. Manufacturing test option.
Should be externally pulled-down for proper
operation.
System Clock. Based on system requirement,
SCLK needs to operate at difference
frequency.
SCLK requires 40/60% duty cycle clock.
+1.8 Volt DC Supply
+3.3 Volt DC Supply
Ground
Reset Input
Reset PHY
MII Management Data Clock
MII Management Data I/O
14
Zarlink Semiconductor Inc.