ZL50050 Datasheet, PDF (65/94 Pages) Zarlink Semiconductor Inc – 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs

ZL50050
Data Sheet
14.7.1 Backplane Input Delay Bits 4-0 (BID[4:0])
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses
to sample each input. Input bit delay adjustment can range up to 7³/₄ bit periods forward, with resolution of ¹/₄ bit
period. The default sampling point is at the ³/₄ bit location.
This can be described as: no. of bits delay = BID[4:0] / 4
For example, if BID[4:0] is set to 10011 (19), the input bit delay = 19 * ¹/₄ = 4³/_4.
When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (¹/₄ to ⁴/₄). BID[4:2]
refers to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from ¹/₄ to ⁴/₄ in ¹/₄ bit increments.
Table 29 illustrates the bit delay and sampling point selection.
BIDn
SMPL_MODE
= LOW
SMPL_MODE
= HIGH
BID4 BID3 BID2 BID1 BID0
Input Data
Bit Delay
Input Data
Bit Delay
Input Data
Sampling
Point
0
0
0
0
0
0 (Default) 0 (Default)
3/4
0
0
0
0
1
1/4
0
4/4
0
0
0
1
0
1/2
0
1/4
0
0
0
1
1
3/4
0
2/4
0
0
1
0
0
1
1
3/4
0
0
1
0
1
1 1/4
1
4/4
0
0
1
1
0
1 1/2
1
1/4
0
0
1
1
1
1 3/4
1
2/4
0
1
0
0
0
2
2
3/4
0
1
0
0
1
2 1/4
2
4/4
0
1
0
1
0
2 1/2
2
1/4
0
1
0
1
1
2 3/4
2
2/4
0
1
1
0
0
3
3
3/4
0
1
1
0
1
3 1/4
3
4/4
0
1
1
1
0
3 1/2
3
1/4
0
1
1
1
1
3 3/4
3
2/4
1
0
0
0
0
4
4
3/4
1
0
0
0
1
4 1/4
4
4/4
1
0
0
1
0
4 1/2
4
1/4
1
0
0
1
1
4 3/4
4
2/4
1
0
1
0
0
5
5
3/4
1
0
1
0
1
5 1/4
5
4/4
1
0
1
1
0
5 1/2
5
1/4
1
0
1
1
1
5 3/4
5
2/4
1
1
0
0
0
6
6
3/4
1
1
0
0
1
6 1/4
6
4/4
1
1
0
1
0
6 1/2
6
1/4
Table 29 - Backplane Input Bit Delay and Sampling Point Programming Table
65
Zarlink Semiconductor Inc.