ZL50050 Datasheet, PDF (26/94 Pages) Zarlink Semiconductor Inc – 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs

ZL50050
Data Sheet
by jitter. There are, however, some cases where data experience more delay than the timing signals. A common
example is when multiple data lines are tied together to form bidirectional buses. The large bus loading may cause
data to be delayed. If this is the case, the optimum sampling point may be 3/4 or 4/4 instead of 1/2. The optimum
sampling point is dependent on the application. The user should optimize the sampling point to achieve the best
jitter tolerance performance.
2.5 Input Clock Jitter Tolerance
Input clock jitter tolerance depends on the data rate. In general, the higher the data rate, the smaller the jitter
tolerance is, because the period of a bit cell is shorter, and the sampling point variation allowance is smaller.
Jitter tolerance can not be accurately represented by just one number. Jitter of the same amplitude but different
frequency spectrum can have different effect on the operation of a device. For example, a device that can tolerate
20 ns of jitter of 10 kHz frequency may only be able to tolerate 10 ns of jitter of 1 MHz frequency. Therefore, jitter
tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the
carrier frequency. In the case of the ZL50050, the input clock is 8.192 MHz, and the jitter associated with this clock
can have the highest frequency component at 4.096 MHz.
For the above reasons, jitter tolerance of the ZL50050 has been characterized at two data rates, 16.384 Mbps and
32.768 Mbps. The lower data rates (2.048Mbps, 4.096 Mbps, 8.192 Mbps) will have the same or better tolerance
than that of the 16.384 Mbps operation. Tolerance of jitter of different frequencies are shown in the “AC Electrical
Characteristics“ section, table “Input Clock Jitter Tolerance“ on page 90. The Jitter Tolerance Improvement Circuit
was enabled (Control Register, bit FBDEN set HIGH, and bits FBD_MODE[2:0] set to 111_B), and the sampling point
was optimized.
2.6 Backward Compatibility with MT90871
The ZL50050 is pin-to-pin compatible with Zarlink’s MT90871 device. To ensure software compatibility between the
two devices, the user must consider the following items:
1. The ZL50050 has enhanced input clock jitter tolerance. To maximize the jitter tolerance, the Frame Boundary
Discriminator (FBD) circuit has to be enabled by setting bits FBDEN and FBD_MODE[2:0] in the Control Regis-
ter HIGH. In MT90871, these bits are un-used. The input data sampling point also needs to be optimized by pro-
gramming all the LIDR and BIDR registers. These are described in details in Section 2.4.
2. When Bit Error Rate (BER) transmission is enabled, all the channels on all same side (Local/Backplane) as the
target BER transmission channel(s) will be unable to switch traffic. Also, the BER Counters (LBCR and BBCR)
will not rollover. They will saturate when they reach their maximum value. These are described in more details in
Section 6.0.
3. The hardware reset signal (RESET) must be de-asserted less than 12 µs after the frame boundary or more than
13µs after the frame boundary, as described in Section 8.3. This can be achieved, for example, by synchroniz-
ing the de-assertion of the reset signal with the input frame pulse.
3.0 Input and Output Offset Programming
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and
Backplane streams. The following sections explain the details of these offset programming features.
3.1 Input Offsets
Control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different frame
boundary with respect to the master frame pulse, FP8i.
The use of Input Channel Delay in combination with Input Bit Delay enables the Ch0 position to be placed
anywhere within a frame to a resolution of 1/4 of the bit period.
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