ZL50050 Datasheet, PDF (1/94 Pages) Zarlink Semiconductor Inc – 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs

ZL50050
8 K-Channel Digital Switch with High Jitter
Tolerance, Per Stream Rate Conversion (2, 4, 8,
16, or 32 Mbps), and 32 Inputs and 32 Outputs
Data Sheet
Features
• 8,192-channel x 8,192-channel non-blocking
unidirectional switching.The Backplane and Local
inputs and outputs can be combined to form a
non-blocking switching matrix with 32 input
streams and 32 output streams
• 4,096-channel x 4,096-channel non-blocking
Backplane input to Local output stream switch
• 4,096-channel x 4,096-channel non-blocking
Local input to Backplane output stream switch
• 4,096-channel x 4,096-channel non-blocking
Backplane input to Backplane output switch
• 4,096-channel x 4,096-channel non-blocking
Local input to Local output stream switch
• Rate conversion on all data paths, Backplane-to-
Local, Local-to-Backplane, Backplane-to-
Backplane and Local-to-Local streams
• Backplane port accepts 16 input and 16 output
ST-BUS streams with data rates of 2.048 Mbps,
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any
combination, or a fixed allocation of 8 input and 8
output streams at 32.768 Mbps
• Local port accepts 16 input and 16 output ST-
BUS streams with data rates of 2.048 Mbps,
January 2006
Ordering Information
ZL50050GAC 196 Ball PBGA Trays
ZL50050GAG2 196 Ball PBGA** Trays
*Pb Free Tin/Silver/Copper
-40°C to +85°C
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any
combination, or a fixed allocation of 8 input and 8
output streams at 32.768 Mbps
• Exceptional input clock jitter tolerance (17ns for
16Mbps or lower data rates, 14ns for 32 Mbps)
• Per-stream channel and bit delay for Local and
Backplane input streams
• Per-stream advancement for Local and Backplane
output streams
• Constant 2-frame throughput delay for frame
integrity
• Per-channel high impedance output control for
Local and Backplane streams
• Per-channel driven-high output control for Local
and Backplane streams
V_{DD_IO} V_{DD_CORE}
V_{SS (GND)}
RESET
ODE
BSTi0-15
Backplane Data Memories
(4,096 channels)
Local
Interface
LSTi0-15
BSTo0-15
BCST0-1
BORS
FP8i
C8i
Backplane
Interface
Backplane
Connection Memory
(4,096 locations)
Local
Connection Memory
(4,096 locations)
Local
Interface
Input
Timing Unit
PLL
Local Data Memories
(4,096 channels)
Microprocessor Interface
and Internal Registers
Output
Timing
Unit
Test Port
LSTo0-15
LCST0-1
LORS
FP8o
FP16o
C8o
C16o
V_{DD_PLL}
DS CS R/W A14-0 DTA D15-0 TMS TDi TDo TCK TRST
Figure 1 - ZL50050 Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.