ZL50050 Datasheet, PDF (43/94 Pages) Zarlink Semiconductor Inc – 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs

ZL50050
Data Sheet
and BE) of the respective connection memories should be set to HIGH to enable the outputs for the selected
channels.
The BER receive channel numbering is not affected by the input channel delay value. It means that the BER
receive circuitry always assume there is no input channel delay, regardless of the values of the BCDR and LCDR
registers. For example, if BER data is received on local input stream 0 channel 3, without input channel delay, the
LBSRR (Local BER Start Receive Register) should be programmed to 3. With input channel delay of 5, however,
the LBSRR should be programmed to 8 (3 + 5) instead.
Note that when BER transmission is enabled, the target channels will carry PRBS data, and the rest of the channels
on all streams of the same side (Local/Backplane) will carry unknown data, which renders that side of the switch
unable to switch traffic during BER Test.
7.0 Microprocessor Port
The 16K switch family supports non-multiplexed Motorola type microprocessor buses. The microprocessor port
consists of a 16-bit parallel data bus (D0-15), a 15-bit address bus (A0-14) and four control signals (CS, DS, R/W
and DTA). The data bus provides access to the internal registers, the Backplane Connection and Data Memories,
and the Local Connection and Data Memories. Each memory has 8,192 locations. See Table 11, Address Map for
Data and Connection Memory Locations (A14 = 1), for the address mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only
be read (but not written) from the microprocessor port.
To prevent the bus’hanging’, in the event of the switch not receiving a master clock, the microprocessor port shall
complete the DTA handshake when accessed, but any data read from the bus will be invalid.
8.0 Device Power-up, Initialization and Reset
8.1 Power-Up Sequence
The recommended power-up sequence is for the V_{DD_IO} supply (nominally +3.3V ) to be established before the
power-up of the V_{DD_PLL} and V_{DD_CORE} supplies (nominally +1.8V). The V_{DD_PLL} and V_{DD_CORE} supplies may be
powered up simultaneously, but neither should 'lead' the V_{DD_IO} supply by more than 0.3 V.
All supplies may be powered-down simultaneously.
8.2 Initialization
Upon power up, the device should be initialized by applying the following sequence:
1. Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller.
2. Set ODE pin to LOW. This configures the LCSTo0-1 output signals to LOW (i.e., setting optional external
output buffers to high impedance), and sets the LSTo0-15 outputs to HIGH or high impedance, dependent
on the LORS input value, and sets the BCSTo0-1 output signals to LOW (i.e., setting optional external out-
put buffers to high impedance), and sets the BSTo0-15 outputs to HIGH or high impedance, dependent on
BORS input value. Refer to Pin Description for details of the LORS and BORS pins.
3. Reset the device by asserting the RESET pin to zero for at least two cycles of the input clock, C8i. A
delay of an additional 250 µs must also be applied before the first microprocessor access is performed
following the de-assertion of the RESET pin; this delay is required for determination of the input frame
pulse format.
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Zarlink Semiconductor Inc.