ZL50050 Datasheet, PDF (61/94 Pages) Zarlink Semiconductor Inc – 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs

ZL50050
Data Sheet
14.5 Local Input Bit Delay Registers (LIDR0 to LIDR15)
Addresses 0023_H to 0032_H.
There are sixteen Local Input Delay Registers (LIDR0 to LIDR15).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and LIDR0 to LIDR15 define the input bit and fractional bit delay of each Local stream. The possible bit
delay adjustment is up to 7³/₄ bits, in steps of ¹/₄ bit.
When the SMPL_MODE bit is HIGH, LIDR0 to LIDR15 define the input bit sampling point as well as the integer bit
delay of each Local stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay can be
adjusted in 1-bit increments from 0 to 7 bits.
The LIDR0 to LIDR15 registers are configured as follows:
LIDRn Bit
(where n = 0 to 15 for Local
Non-32 Mbps Mode, n = 0 to 7
for Local 32 Mbps Mode)
Name
Reset
Value
Description
15:5
Reserved
0
Reserved
Must be set to 0 for normal operation
4:0
LID[4:0]
0 Local Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit and fractional bit delay value (0
to 7³/₄).
When SMPL_MODE = HIGH, the binary value of LID[1:0]
refers to the input bit sampling point (¹/₄ to ⁴/₄). LID[4:2]
refers to the integer bit delay value (0 to 7 bits).
Table 24 - Local Input Bit Delay Register (LIDRn) Bits
14.5.1 Local Input Delay Bits 4-0 (LID[4:0])
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 7³/₄ bit periods forward, with resolution of ¹/₄ bit
period. The default sampling point is at the ³/₄ bit location.
This can be described as: no. of bits delay = LID[4:0] / 4
For example, if LID[4:0] is set to 10011 (19), the input bit delay = 19 * ¹/₄ = 4³/₄.
When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point (¹/₄ to ⁴/₄). LID[4:2]
refers to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from ¹/₄ to ⁴/₄ in ¹/₄ bit increments.
Table 25 illustrates the bit delay and sampling point selection.
LIDn
SMPL_MODE
= LOW
SMPL_MODE
= HIGH
LID4 LID3 LID2
0
0
0
0
0
0
LID1 LID0
0
0
0
1
Input Data
Bit Delay
0 (Default)
1/4
Input Data
Bit Delay
0 (Default)
0
Input Data
Sampling
Point
3/4
4/4
Table 25 - Local Input Bit Delay and Sampling Point Programming Table
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Zarlink Semiconductor Inc.