MT92210 Datasheet, PDF (52/175 Pages) Zarlink Semiconductor Inc – 1023 Channel Voice Over IP Processor

Data Sheet
MT92210
performed on the packet and that no HDLC address or control byte insertion will be done, it is otherwise identical to
the RX HDLC Channel Structure.
RX CPU
Circular Buffer
(1 per Buffer)
RXCIRC2-3
RX HDLC
Circular Buffer
(1 per Stream)
RXCIRC5
RX xxPCM
Circular Buffer
(1 per Bearer)
RXCIRC4
RX CPU Buffer
Control Table (1
per Buffer)
RXCIRC1
RX HDLC
Stream/Buffer
Control Table
(1 per Stream)
RXCIRC0
Extended PDV
Monitoring
Structure (0-1
per PDV
Absorption
Structure)
DISAS4
RTP-only structures
RX RTP CPU
Channel Structure
(1 per channel)
DISAS11
Payload
Type/Marker Bit
Table (1 per
connection) PTM1
RX RTP HDLC
Channel
Structure (1 per
channel)
DISAS10
RTP Common
PDV Absorption
Structure (1 per
N channels)
DISAS9
Note: The Packet Disassembly
process has interactions with all the
structures on this page. The arrows
have not all been drawn for clarity.
RX RTP xxPCM
Channel
Structure (1 per
channel) DISAS5
CN Packet
Conversion
Lookup Table
(global) RXTDM3
Packet
Disassembly
Process
RX RTP
Connection
Structure (1 per
connection)
DISAS8
Event Report
Queue (global)
RXQUEUE0-4
Packet
Disassembly
Control FIFO
(global)
Packet
Disassembly Data
FIFO (global)
Packet Disassembly Process:
Performs dejittering on xxPCM data,
copies payload into circular buffer,
performs policing on HDLC & CPU
channels, reports errors & events in
the Event Report Queue.
Clock Recovery
Event Queue (2
of them, global)
CLKRECOV0-2
Figure 27 - Rx Flow 3
Once the bytes have been copied into the correct circular buffers, only the RX TDM process remains. The RX TDM
process is not event-driven with regards to the other processes: by following the Data Flow, we see that, from the
Packet Reassembly Process, each process has been triggered by the previous one completing and handing it over
the packet. The RX TDM only communicates with the Packet Disassembly process through the TDM pointer.
The RX TDM process reads bytes out of the PCM and HDLC circular buffers and places them onto the H.110 bus.
Each frame it reads one byte out of each xxPCM circular buffer and places it on the appropriate TSST; it uses a
channel association memory to make this connection. It also compensates for underruns and packet losses by
inserting SSRAM Tone Buffers, SDRAM Silence Buffers or Padding Octets. In HDLC, when there is no data to be
sent on a stream, it sends the idle code.
Zarlink Semiconductor Inc.
52