MT92210 Datasheet, PDF (25/175 Pages) Zarlink Semiconductor Inc – 1023 Channel Voice Over IP Processor

Data Sheet
MT92210
destination. Packets from the packet assembly module can be routed to any one of the TX link buffers or to the
packet identifier for internal loopback functionality.
Packets going to the disassembly module use a similar scheme: a 2 K-byte memory is used for the packets and a
128-byte memory for the handles.
Near the TX link layer interface, the network module uses 512-byte buffers to transfer packets between the SDRAM
and the link layer interfaces. There are 4 buffers used for this purpose: 1 destined to TX link A, 1 to TX link B, 1 from
RX link A and 1 from RX link B. These buffers can be smaller because the system operates flawlessly even if the
entire packet is not contained in the buffer at any one time.
Cells contained in external memory are stored in the SSRAM and free cells are allocated as the various modules
within the chip request them. The cells are also managed in a linked list, in the same way as the packet are.
However, since each cell is individual (i.e. not part of a packet comprised of many blocks) they are only linked when
they are free: when a cell is allocated and contains valid data, its link is not used. Whenever cells are allocated, the
pointer to the cell is added to a cell queue, which contains all cells going to a given destination. The following
figures indicate the format of raw cells in queues, depending on whether the cell is allocated or free:
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b 15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
+0
+4
+8
+C
+10
+14
+18
+1C
+20
+24
+28
+2C
+30
+34
+38
Multicast Sum
Cell Header[31:0]
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
Cell Payload
PN
AAL5 VC Number [15:0]
+3C
Figure 9 - Raw Cell Format (used cell)
Field
Description
Multicast Sum
Used in TX. When Cell is queued in multiple TX queues this is decremented each
time the cell is sent and the TX queue that decrements it to 0 frees the cell memory.
AAL5 VC Number This points to a Packet Reassembly structure.
PN
Port Number. Used in RX. Source port of this cell. Used to indicate, in the RX AAL0
FIFO, where cells originated. “00” = RX port A, “01” = RX port B; “11” = TX CPU.
Table 9 - Fields and Description
Zarlink Semiconductor Inc.
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