MT92210 Datasheet, PDF (15/175 Pages) Zarlink Semiconductor Inc – 1023 Channel Voice Over IP Processor

Data Sheet
MT92210
3.2.1.2 Interrupt Servicing
When interrupt2 is asserted (‘inetrrupt2’ pin):
1. Read the interrupt flags to ascertain the module raising the interrupt. The CPU module interrupt flag is located
in register inetrrupt_flags(210h), this bit is named cpureg_interrupt_active.
2. If the cpureg_interrupt_active bit is set, check the source of the CPU interrupt by reading the ‘status0’ register
at 102h, either internal_read_timeout_sar, and/or inmo_read_done, and/or interrnal_read_timeout_net
3. To de-assert the interrupt the user must write 1 to corresponding bit in register 102h, ether
internal_read_timeout_sar, and/or inmo_read_done, and/or internal_read_timeout_net. Only then will the inter-
rupt be de-asserted.
b 15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Status Bits
AND
OR
internal interrupt
Interrupt Enable Bits
Global Service Register (0210h)
Interrupt1 Enable (0218h)
AND
OR
AND
OR
Interrupt2 Enable (021Ch)
Interrupt
Frequency
Controler
interrupt2_active_level
interrupt2
interrupt1_active_level
interrupt1
Figure 2 - Internal Interrupt Network
Zarlink Semiconductor Inc.
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