MDS105 Datasheet, PDF (28/35 Pages) Zarlink Semiconductor Inc – Unmanaged 5-Port 10/100 Mbps Ethernet Switch

MDS105
13.4 Clock Frequency Specifications
Symbol
C1
C2
C3
C4
C5
C6
Parameter
SCLK - Core System Clock Input
M_CLK - RMII Port Clock
M4_REFCLK - MII Reference Clock
L_CLK - Frame Buffer Memory Clock
M_MDC - MII Management Data Clock
SCL - I²C Data Clock
(Hz)
Note:
50 M
50 M
25 M
50 M L_CLK = SCLK
1.56 M M_MDC = SCLK/32
50 K SCL = M_CLK/1000
Suggestion Clock rate for various configurations:
Data Sheet
Configuration
Port 0-3
10 M RMII
100 M RMII
100 M RMII
Port 4
10/100 M MII
Not Used
10/100 M MII
Input
SCLK
25 M
50 M
50 M
M_CLK
(RMII)
50 M
50 M
50 M
L_CLK
=SCLK
=SCLK
=SCLK
Output
M_MDC
=SCLK/32
=SCLK/32
=SCLK/32
SCL
50 K
50 K
50 K
28
Zarlink Semiconductor Inc.