MDS105 Datasheet, PDF (11/35 Pages) Zarlink Semiconductor Inc – Unmanaged 5-Port 10/100 Mbps Ethernet Switch

MDS105
Data Sheet
4.0 Buffer Management
The MDS105 stores each input packet into the external frame buffer memory while determining the destination the
packet is to be forwarded to. The total number of packets that can be stored in the frame buffer memory depends
upon the size of the external SBRAM that is utilized. For a 256 KB SBRAM the MDS105 can buffer 170 packets.
For a 512 KB SBRAM the MDS105 can buffer 340 packets.
In order to provide good quality of service characteristics, the MDS105 must carefully allocate the available buffer
space. Such careful allocation can be accomplished using the external EEPROM to load the appropriate values into
the MDS105 configuration registers. The Low-Drop Precedence Buffer Threshold (LPBT) register assures that
traffic designated as low-drop actually receives reserved buffer space. The designer can set the minimum number
of buffers reserved for low-drop unicast traffic, by setting this register with a value between 0 and 255. Unreserved
buffers are treated as shared, and are accessible to all types of incoming traffic.
To set the maximum number of buffers permitted for all multicast packets, use the Multicast Buffer Control Register
(MBCR). Unlike the LPBT register, the MBCR register does not define a reserved area of buffer memory, but
instead provides a bound on the number of multicast packets that can be buffered at any one time.
During operation the MDS105 will continuously monitor the amount of frame buffer memory that is available, and
when the unused buffer space falls below a designer configurable threshold, the MDS105 will initiate flow control if
enabled or WRED if not. This threshold is set using the FCB Buffer Low Threshold (FCBST) register.
5.0 Virtual LANs
The MDS105 provides the designer the ability to define a single port-based Virtual LAN (VLAN) for each of the five
ports. This VLAN is individually defined for each port using the Port Control Registers (ECR1Px[6:4]). Bits [6:4]
allow the designer to define a VLAN ID (value between 0 – 3) for each port.
When packets arrive at an input of the MDS105, the search engine will determine the VLAN ID for that port, and
then determine which of the other ports are also members of that VLAN by matching their assigned VLAN ID
values. The packet will then be transmitted to each port with the same VLAN ID as the source port.
6.0 Port Trunking
Port trunking allows the designer to configure the MDS105, such that ports 0 and 1 are defined as a single logical
port. This provides a 200 Mbps link to a switch or server utilizing two 100 Mbps ports in parallel.
Ports 0 and 1 can be trunked by pulling the TRUNK_EN pin to the high state. In this mode, the source MAC
addresses of all packets received from the trunk are checked against the MCT database to ensure that they have a
port ID of 0 or 1. Packets that have a port ID other than 0 and 1 will cause the MDS105 to learn the new MAC
address for this port change.
On transmission, the trunk port is determined by hashing the source and destination MAC addresses. This provides
a mapping between each MAC address and an associated trunk port. Subsequent packets with the same MAC
address will always utilize the same trunk port.
The MDS105 also provides a safe fail-over mode for port trunking. If one of the two ports goes down, as identified
by the port’s link status signal, then the MDS105 will switch all traffic over to the remaining port in the trunk. Thus,
the trunk link is maintained, albeit at a lower effective bandwidth.
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Zarlink Semiconductor Inc.