MDS105 Datasheet, PDF (14/35 Pages) Zarlink Semiconductor Inc – Unmanaged 5-Port 10/100 Mbps Ethernet Switch

MDS105
Data Sheet
11.0 Configuration Register Definitions
The MDS105 registers can be accessed via the parallel interface and/or the I²C interface. Some registers are only
accessible through the parallel interface. The access method for each register is listed in the individual register
definitions. Each register is 8 bits wide.
11.1 GCR - Global Control Register
• Access: parallel interface, Write Only
• Address: h30
Bit 0
Bit 1
Bit 2
Bit 3
Bit [7:4]
Save configuration into EEPROM
Write '1' followed by a '0'
Save configuration into EEPROM and reset
system
Write '1' (self-clearing due to reset)
Start Built-In Self-Test (BIST)
Write '1' followed by a '0'
Reset system
Write '1' (self-clearing due to reset)
Reserved
11.2 DCR - Device Status and Signature Register
• Access: parallel interface, Read Only
• Address: h31
Bit 0
Bit 1
Bit 2
Bit 3
Bits [5:4]
Bits [7:6]
Busy writing configuration from I²C
1: Activity
0: No Activity
Busy reading configuration from I²C
1: Activity
0: No Activity
Built-In Self-Test (BIST) in progress
1: BIST In-Progress
0: Normal Mode
RAM error during BIST
1: RAM Error
0: No Error
Reserved
Revision number
00: Initial Silicon
01: Second Silicon
(Default = 0)
(Default = 0)
(Default = 0)
(Default = 0)
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Zarlink Semiconductor Inc.