YMF715E Datasheet, PDF (46/54 Pages) YAMAHA CORPORATION – OPL3 Single-chip Audio System 3

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AC Characteristics
CPU Interface & DMA BUS Cycle :Fig.1,2,3,4,5,6,7,8
Item
Symbol Min. Typ. Max. Unit
/DACK inactive to /IOW, /IOR falling edge
/DACK active from /IOW, /IOR rising edge
Address set up to /IOW, /IOR active
Address hold to /IOW, /IOR inactive
/IOW Write Pulse Width
Write Data set up to /IOW active
Write Data hold to /IOW inactive
/IOR Read Pulse Width
Read Data access time
Read Data hold from /IOR inactive
DRQ hold from /IOW, /IOR falling edge
/DACK set up to /IOW, /IOR falling edge
/DACK hold to /IOW, /IOR rising edge
Time between rising edge of /IOW, /IOR to next
falling edge of /IOW, /IOR
t_AKS
50
t_AKH
10
t_AS
40
t_AH
10
t_WW
90
t_WDS
20
t_WDH
10
t_RW
90
t_ACC
t_RDH
0
t_DGH
0
t_SF
25
t_HR
25
t_NX
100
ns
ns
ns
ns
ns
ns
ns
ns
80 ns
ns
20 ns
ns
ns
ns
Valid Address from /SYNCS or /MCS or /CDCS1-0 t_EX1
70(90) * ns
/SYNCS or /MCS or /CDCS1-0 hold to Valid Address
t_EX2
70(90) * ns
RESET Pulse Width
t_RST
90
Жs
ɹNote : DV_SS=AV_SS=0[V], T_OP=0~70ˆ, DV_DD=5.0ʶ0.25[V] or 3.3ʶ0.30[V], AV_DD=5.0[V]
*... The value into the brackets is specified at DV_DD=3.3ʶ0.30[V].
Serial Audio (Zoomed Video) Interface Input :Fig.9
Item
Symbol
Condition
Min. Typ. Max. Unit
BCLK Cycle
f_BCK
32fs 48fs 64fs kHz
BCLK Duty
D_BCLK
40
50
60 %
LRCK Hold Time
t_LRH BCLKË¢/LRCK
-120
120 ns
SIN Set up Time
t_DS BCLKË¢/SIN
20
ns
SIN Hold Time
t_DH BCLKË¢/SIN
20
ns
CLKO Frequency
f_CLKO33
33.8688
MHz
CLKO Duty
D_CLKO33
f₃₃=50%
40
50
60 %
ɹNote : DV_SS=AV_SS=0[V], T_OP=0~70ˆ, DV_DD=5.0ʶ0.25[V] or 3.3ʶ0.30[V], AV_DD=5.0[V]
Duty Search Point is 1/2 DV_DD.
May 21, 1997
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