XC17V00_08 Datasheet, PDF (9/15 Pages) Xilinx, Inc – XC17V00 Series Configuration PROMs

R
XC17V00 Series Configuration PROMs
X-Ref Target - Figure 3
DOUT
FPGA
Modes⁽¹⁾
VCC
4.7K
VCC
4.7K
VCC
(2)
OPTIONAL
Daisy-chained
FPGAs with
different
configurations
OPTIONAL
Slave FPGAs
with identical
configurations
VCC
VCC
DIN
CCLK
DONE
INIT
PROGRAM
VCC Vpp
DATA
BUSY
CLK ^First
CE ^{PROM CEO}
OE/RESET
VCC Vpp
BUSY
DATA
CLK Cascaded
CE
PROM
OE/RESET
(Low Resets the Address Pointer)
(1) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide.
(2) For specific DONE resistor recommendations, refer to the appropriate FPGA data sheet or user guide.
Master Serial Mode
Modes⁽³⁾
CS
WRITE
FPGA
BUSY
CCLK
PROGRAM D[0:7]
DONE
INIT
I/O⁽¹⁾
I/O⁽¹⁾
1K ^1K
VCC
(2)
External
Osc⁽⁴⁾
VCC
3.3V
4.7K
8
VCC Vpp
BUSY
First
CLK ^PROM
D[0:7]
CEO
CE
OE/RESET
VCC
VCC Vpp
BUSY
CLK
Second
PROM
D[0:7]
CEO
CE
OE/RESET
(1) CS and WRITE must be pulled down to be used as I/O. One option is shown.
(2) For specific DONE resistor recommendations, refer to the appropriate FPGA data sheet or user guide.
(3) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide.
(4) External oscillator required for FPGA slave SelectMAP modes.
SelectMAP Mode, XC17V16 and XC17V08⁽¹⁾ only.
Figure 3: (a) Master Serial Mode (b) SelectMAP Mode
(dotted lines indicate optional connection)
Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
DS073_03_102708
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
9