XC17V00_08 Datasheet, PDF (11/15 Pages) Xilinx, Inc – XC17V00 Series Configuration PROMs

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XC17V00 Series Configuration PROMs
AC Characteristics over Operating Condition for XC17V04, XC17V02, and
XC17V01
X-Ref Target - Figure 4
TCEH
CE
RESET/OE
CLK
DATA
TSCE
TOE
TCE
TLC
THC
TCAC
TSCE
TCYC
THOE
TOH
TDF
THCE
TOH
Notes:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high
RESET polarity. Timing specifications are identical for both polarity settings.
2 The diagram shows timing relationships. The diagram is not reflective of actual FPGA signal sequences. See the appropriate
FPGA data sheet or user guide for actual configuration signal sequences.
DS073_04_14102005
Symbol
Description
Min
Max
T_OE
T_CE
T_CAC
T_DF
T_OH
T_CYC
T_LC
T_HC
T_SCE
T_HCE
T_HOE
T_CEH
OE to data delay
CE to data delay
CLK to data delay
CE or OE to data float delay^(2,3)
Data hold from CE, OE, or CLK⁽³⁾
Clock periods
CLK Low time⁽³⁾
CLK High time⁽³⁾
CE setup time to CLK (to guarantee proper counting)
CE hold time to CLK (to guarantee proper counting)
OE hold time (guarantees counters are reset)
CE High time (guarantees counters are reset)
–
30
–
45
–
45
–
50
0
–
67
–
25
–
25
–
25
–
0
–
25
–
20
–
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V_IL = 0.0V and V_IH = 3.0V.
5. If T_CEH High, 2 μs, T_CE = 2 μs.
6. If T_HOE High, 2 μs, T_OE = 2 μs.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
11