XC17V00_08 Datasheet, PDF (7/15 Pages) Xilinx, Inc – XC17V00 Series Configuration PROMs

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XC17V00 Series Configuration PROMs
Controlling PROMs
Connecting the FPGA device with the PROM.
• The DATA output(s) of the PROM(s) drives the
configuration data input(s) of the lead FPGA device.
• The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
• The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
• The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V_CC glitch.
• The PROM CE input is best connected to the FPGA
DONE pin(s) and a pullup resistor. CE can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
15 mA maximum.
• SelectMAP mode is similar to Slave Serial mode. The
DATA is clocked out of the PROM one byte per CCLK
instead of one bit per CCLK cycle. See FPGA data
sheets for special configuration requirements.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration
program from an external memory. The Xilinx PROMs have
been designed for compatibility with the Master Serial
mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA mode-
select pins are Low (M0=0, M1=0, M2=0). Data is read from
the PROM sequentially on a single data line.
Synchronization is provided by the rising edge of the
temporary signal CCLK, which is generated during
configuration.
Master Serial Mode provides a simple configuration
interface. Only one serial data line, two control lines, and
one clock line are required to configure an FPGA. Data from
the PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up/down resistor or keeper circuit.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories,
cascaded PROMs provide additional memory. After the last
bit from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See Figure 3.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the FPGA PROGRAM pin
goes Low, assuming the PROM reset polarity option has
been inverted.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high impedance
state regardless of the state of the OE input.
Programming
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
Selecting Reset Polarity and
Configuration Modes
The OE/RESET input polarity is programmable on all
XC17V00 PROMs. In addition, the XC17V08 and XC17V16
can accommodate either serial or parallel configuration
mode. The reset polarity and configuration mode are
selectable through the programmer software. For
compatibility with Xilinx FPGAs, the OE/RESET polarity
must be programmed with RESET active-Low.
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
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