XC17V00_08 Datasheet, PDF (13/15 Pages) Xilinx, Inc – XC17V00 Series Configuration PROMs

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XC17V00 Series Configuration PROMs
AC Characteristics over Operating Condition When Cascading
X-Ref Target - Figure 6
RESET/OE
CE
CLK
DATA
TCDF
Last Bit
TOCK
TOCE
TOOE
CEO
Notes:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high
RESET polarity. Timing specifications are identical for both polarity settings.
2 The diagram shows timing of the First Bit and Last Bit for one PROM with respect to signals involved in a cascaded situation.
The diagram does not show timing of data as one PROM transfers control to the next PROM. The shown timing information must
be applied appropriately to each PROM in a cascaded situation to understand the timing of data during the transfer of control
from one PROM to the next.
First Bit
DS026_07_102005
Symbol
T_CDF
T_OCK
T_OCE
T_OOE
Description
CLK to data float delay^(2,3)
CLK to CEO delay⁽³⁾
CE to CEO delay⁽³⁾
RESET/OE to CEO delay⁽³⁾
Min
Max
–
50
–
30
–
35
–
30
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V_IL = 0.0V and V_IH = 3.0V.
Units
ns
ns
ns
ns
Ordering Information
Device Number
XC17V16
XC17V04
XC17V01
XC17V16 PC44 C
Package Type
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
VO8 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
Operating Range/Processing
C = Commercial (T_A = 0° to +70°C)
I = Industrial (T_A = –40° to +85°C)
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
13