XC17V00 Datasheet, PDF (9/12 Pages) Xilinx, Inc – XC17V00 Series Configuration

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XC17V00 Series Configuration PROM
AC Characteristics Over Operating Condition for XC17V04, XC17V02, and
XC17V01
CE
RESET/OE
CLK
DATA
TSCE
TOE
TCE
TLC
THC
TCAC
TSCE
TCYC
THOE
TOH
TDF
THCE
TOH
DS073_04_072600
Symbol
Description
Min
Max
T_OE OE to data delay
-
30
T_CE CE to data delay
-
45
T_CAC
T_DF
T_OH
CLK to data delay
CE or OE to data float delay^(2,3)
Data hold from CE, OE, or CLK⁽³⁾
-
45
-
50
0
-
T_CYC
T_LC
T_HC
Clock periods
CLK Low time⁽³⁾
CLK High time⁽³⁾
67
-
25
-
25
-
T_SCE CE setup time to CLK (to guarantee proper counting)
25
-
T_HCE CE hold time to CLK (to guarantee proper counting)
0
-
T_HOE OE hold time (guarantees counters are reset)
25
-
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V_IL = 0.0V and V_IH = 3.0V.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS073 (v1.0) July 26, 2000
www.xilinx.com
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