XC17V00 Datasheet, PDF (6/12 Pages) Xilinx, Inc – XC17V00 Series Configuration

XC17V00 Series Configuration PROM
R
DOUT
FPGA
Modes*
VCC
4.7K
VCC
**
OPTIONAL
Daisy-chained
FPGAs with
different
configurations
OPTIONAL
Slave FPGAs
with identical
configurations
Vcc Vcco
DIN
CCLK
DONE
INIT
PROGRAM
VCC VCCO
DATA
BUSY
CLK ^First
CE ^{PROM CEO}
OE/RESET
(Low Resets the Address Pointer)
*For Mode pin connections, refer to the appropriate FPGA data sheet.
**Virtex, Virtex-E is 300 ohms, all others are 4.7K.
Master Serial Mode
BUSY
DATA
CLK Cascaded
CE
PROM
OE/RESET
CS
Modes***
WRITE
VIRTEX
Select MAP
BUSY
CCLK
D[0:7]
DONE
INIT
I/O*
I/O*
1K ^1K
VCC
**
VCC VCCO
External Osc
3.3V
4.7K
8
VCC VCCO
BUSY
XC17Vxx
CLK
D[0:7]
CEO
CE
OE/RESET
*CS and WRITE must be pulled down to be used as I/O. One option is shown.
**Virtex, Virtex-E is 300 ohms, all others are 4.7K.
***For Mode pin connections, refer to the appropriate FPGA data sheet.
Virtex Select MAP Mode, XC17V16 and XC17V08 only.
DS073_03_072600
Figure 3: (a) Master Serial Mode (b) Virtex SelectMAP Mode
(dotted lines indicates optional connection)
6
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DS073 (v1.0) July 26, 2000
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Advance Product Specification