XC17V00 Datasheet, PDF (4/12 Pages) Xilinx, Inc – XC17V00 Series Configuration

XC17V00 Series Configuration PROM
PROM Pinouts for XC17V04, XC17V02, and
XC17V01
8-pin 20-pin 20-pin 44-pin 44-pin
Pin Name VOIC SOIC PLCC VQFP PLCC
DATA
1
1
2
40
2
CLK
2
3
4
43
5
RESET/OE
3
8
6
13
19
(OE/RESET)
CE
4
10
8
15
21
GND
5
11
10 18, 41 24, 3
CEO
6
13
14
21
27
V_PP
7
18
17
35
41
V_CC
8
20
20
38
44
Capacity
Devices
XC17V04
XC17V02
XC17V01
Configuration Bits
4,194,304
2,701,312
1,679,360
Xilinx FPGAs and Compatible PROMs
Device
Configuration
Bits
PROM
XCV50
559,200
XC17V01
XCV100
781,216
XC17V01
XCV150
1,040,096
XC17V01
XCV200
1,335,840
XC17V01
XCV300
1,751,808
XC17V02
XCV400
2,546,048
XC17V02
XCV600
3,607,968
XC17V04
XCV800
4,715,616
XC17V08
XCV1000
6,127,744
XC17V08
XCV50E
630,048
XC17V01
XCV100E
863,840
XC17V01
XCV200E
1,442,106
XC17V01
XCV300E
1,875,648
XC17V02
XCV400E
2,693,440
XC17V02
XCV405E
3,340,400
XC17V04
R
Xilinx FPGAs and Compatible PROMs
Device
Configuration
Bits
PROM
XCV600E
3,961,632
XC17V04
XCV812E
6,519,648
XC17V08
XCV1000E
6,587,520
XC17V08
XCV1600E
8,308,992
XC17V08
XCV2000E
10,159,648
XC17V16
XCV2600E
12,922,336
XC17V16
XCV3200E
16,283,712
XC17V16
Notes:
1. The suggested PROM is determined by compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.
Controlling PROMs
Connecting the FPGA device with the PROM.
• The DATA output(s) of the of the PROM(s) drives the
D_IN input of the lead FPGA device.
• The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
• The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
• The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V_CC glitch.
Other methods—such as driving RESET/OE from LDC
or system reset—assume the PROM internal
power-on-reset is always in step with the FPGA’s
internal power-on-reset. This may not be a safe
assumption.
• The PROM CE input can be driven from either the LDC
or DONE pins. Using LDC avoids potential contention
on the D_IN pin.
• The CE input of the lead (or only) PROM is driven by
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC can be used to drive CE, but must then be
unconditionally High during user operation. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
• SelectMAP mode is similar to Slave Serial mode. The
DATA is clocked out of the PROM one byte per CCLK
instead of one bit per CCLK cycle. See FPGA data
sheets for special configuration requirements.
4
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DS073 (v1.0) July 26, 2000
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Advance Product Specification