XC17V00 Datasheet, PDF (10/12 Pages) Xilinx, Inc – XC17V00 Series Configuration

XC17V00 Series Configuration PROM
R
AC Characteristics Over Operating Condition for XC17V16 and XC17V08
CE
RESET/OE
CLK
DATA
BUSY
TSCE
TLC
THC
TOE
TCE
TSBUSY
TCAC
THBUSY
TSCE
TCYC
THOE
TOH
TDF
TOH
THCE
DS073_05_072600
Symbol
Description
Min
Max
T_OE OE to data delay
-
15
T_CE
T_CAC
CE to data delay
CLK to data delay⁽²⁾
-
20
-
20
T_DF CE or OE to data float delay^(3,4)
T_OH Data hold from CE, OE, or CLK⁽⁴⁾
-
35
0
-
T_CYC
T_LC
T_HC
Clock periods
CLK Low time⁽⁴⁾
CLK High time⁽⁴⁾
67
-
25
-
25
-
T_SCE CE setup time to CLK (to guarantee proper counting)
25
-
T_HCE CE hold time to CLK (to guarantee proper counting)
0
-
T_HOE OE hold time (guarantees counters are reset)
25
-
T_SBUSY BUSY setup time
5
-
T_HBUSY BUSY hold time
5
-
T_WKU V_CC reached normal supply voltage range to output valid
100
-
Notes:
1. AC test load = 50 pF.
2. When BUSY = 0.
3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
4. Guaranteed by design, not tested.
5. All AC parameters are measured with V_IL = 0.0V and V_IH = 3.0V.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
10
www.xilinx.com
DS073 (v1.0) July 26, 2000
1-800-255-7778
Advance Product Specification