DS023 Datasheet, PDF (8/8 Pages) Xilinx, Inc – Lowest power 32 macrocell CPLD

XCR3032XL 32 Macrocell CPLD
R
Revision History
The following table shows the revision history for this document.
Date
11/18/00
02/05/01
04/11/01
04/19/01
08/27/01
01/08/02
06/27/02
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
Revision
Initial Xilinx release.
Removed Timing Model.
Update TSUF spec to meet UMC characterization data. Added Icc vs. Freq. numbers,
Table 1 and updated Figure 1. Added Typical I/V curve, Figure 2; added Table 2: Total User
I/O; changed V_OH spec.
Updated Typical I/V curve, Figure 2: added voltage levels.
Changed from Advance to Preliminary; updated DC Electrical Characteristics; AC Electrical
Characteristics; Internal Timing Parameters; added Derating Curve; added -10 industrial
packages. Added 200 MHz to Figure 1 and Table 1. changed -5 F_SYSTEM to 200 MHz, -5 T_F
to 0.5 ns.
Updated T_HI spec to correct a typo. Added single p-term setup time (T_SU1) to AC Table,
renamed T_SU to T_SU2 for setup time through the OR array. Updated AC Load Circuit diagram
to more closely resemble true test conditions, added note for T_POD delay
measurement.Updated note 5 in AC Characteristics table lowering typical current draw
during configuration.
Added voltage and temperature to Figure 2. Increased -5 T_PCO to 6.0 (from 5.5 ns) by
adding T_PTCK parameter to internal timing model.
8
www.xilinx.com
DS023 (v1.6) June 27, 2002
1-800-255-7778
Preliminary Product Specification