DS023 Datasheet, PDF (4/8 Pages) Xilinx, Inc – Lowest power 32 macrocell CPLD

XCR3032XL 32 Macrocell CPLD
R
Internal Timing Parameters^(1,2)
-5
Symbol
Parameter
Min. Max.
Buffer Delays
T_IN
Input buffer delay
-
0.7
T_FIN
Fast Input buffer delay
-
2.2
T_GCK
Global Clock buffer delay
-
0.7
T_OUT
Output buffer delay
-
1.8
T_EN
Output buffer enable/disable delay
-
4.5
Internal Register, Product Term, and Combinatorial Delays
T_LDI
Latch transparent delay
T_SUI
Register setup time
T_HI
Register hold time
T_ECSU
Register clock enable setup time
T_ECHO
Register clock enable hold time
T_COI
Register clock to output delay
T_AOI
Register async. S/R to output delay
T_RAI
Register async. recovery
T_PTCK
Product term clock delay
T_LOGI1 Internal logic delay (single p-term)
T_LOGI2 Internal logic delay (PLA OR term)
Feedback Delays
-
1.3
1.0
-
0.3
-
2.0
-
3.0
-
-
1.0
-
2.0
-
3.5
-
2.5
-
2.0
-
2.5
T_F
ZIA delay
Time Adders
-
0.5
T_LOGI3
Fold-back NAND delay
-
2.0
T_UDA
Universal delay
-
1.2
T_SLEW
Slew rate limited delay
-
4.0
Notes:
1. These parameters guaranteed by design and characterization, not testing.
2. See XPLA3 family data sheet (DS012) for timing model.
-7
-10
Min. Max. Min. Max. Unit
-
1.6
-
2.2
ns
-
3.0
-
3.1
ns
-
1.0
-
1.3
ns
-
2.7
-
3.6
ns
-
5.0
-
5.7
ns
-
1.6
-
2.0
ns
1.0
-
1.2
-
ns
0.5
-
0.7
-
ns
2.5
-
3.0
-
ns
4.5
-
5.5
-
ns
-
1.3
-
1.6
ns
-
2.3
-
2.1
ns
-
5.0
-
6.0
ns
-
2.7
-
3.3
ns
-
2.7
-
3.3
ns
-
3.2
-
4.2
ns
-
2.9
-
3.5
ns
-
2.5
-
3.0
ns
-
2.0
-
2.5
ns
-
5.0
-
6.0
ns
4
www.xilinx.com
DS023 (v1.6) June 27, 2002
1-800-255-7778
Preliminary Product Specification