XC4VLX15 Datasheet, PDF (7/10 Pages) Xilinx, Inc – High-performance logic applications solution

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Virtex-4 Family Overview
One or Two PowerPC 405 Processor Cores
• 32-bit Harvard Architecture
• 5-Stage Execution Pipeline
• Integrated 16KB Level 1 Instruction Cache and 16KB
Level 1 Data Cache
- Integrated Level 1 Cache Parity Generation and
Checking
• CoreConnect™ Bus Architecture
• Efficient, high-performance on-chip memory (OCM)
interface to block RAM
• PLB Synchronization Logic (Enables Non-Integer
CPU-to-PLB Clock Ratios)
• Auxiliary Processor Unit (APU) Interface and Integrated
APU Controller
- Optimized FPGA-based Coprocessor connection
· Automatic decode of PowerPC floating-point
instructions
- Allows custom instructions (Decode for up to eight
instructions)
- Extremely efficient microcontroller-style interfacing
Two or Four Tri-Mode (10/100/1000 Mb/s)
Ethernet Media Access Control (MAC) Cores
• IEEE 802.3-2000 Compliant
• MII/GMII Interface or SGMII (when used with RocketIO
Transceivers)
• Can Operate Independent of PowerPC processor
• Half or Full Duplex
• Supports Jumbo Frames
• 1000 Base-X PCS/PMA: When used with RocketIO
MGT can provide complete 1000 Base-X
implementation on-chip
Intellectual Property Cores
Xilinx offers IP cores for commonly used complex functions
including DSP, bus interfaces, processors, and processor
peripherals. Using Xilinx LogiCORE™ products and cores
from third party AllianceCORE participants, customers can
shorten development time, reduce design risk, and obtain
superior performance for their designs. Additionally, our
CORE Generator™ system allows customers to implement
IP cores into Virtex-4 FPGAs with predictable and repeat-
able performance. It offers a simple user interface to gener-
ate parameter-based cores optimized for our FPGAs.
The System Generator for DSP tool allows system archi-
tects to quickly model and implement DSP functions using
handcrafted IP, and features an interface to third-party sys-
tem level DSP design tools. System Generator for DSP
implements many of the high-performance DSP cores sup-
porting Virtex-4 FPGAs including the Xilinx Forward Error
Correction Solution with Interleaver/De-interleaver,
Reed-Solomon encoder/decoders, and Viterbi decoders.
These are ideal for creating highly-flexible, concatenated
codecs to support the communications market.
Industry leading connectivity and networking IP cores
include the electronics industry's first Advanced Switching
product, leading-edge PCI Express, Serial RapidIO, Fibre
Channel, and 10Gb Ethernet cores that include Virtex-4
RocketIO multi-gigabit serial interfaces. The Xilinx SPI-4.2
IP core utilizes the Virtex-4 embedded ChipSync technol-
ogy to implement dynamic phase alignment for high-perfor-
mance source-synchronous operation.
MicroBlaze™ 32-bit core provides the industry's fastest soft
processing solution for building complex systems for the
networking, telecommunication, data communication,
embedded and consumer markets. The MicroBlaze proces-
sor features a RISC architecture with Harvard-style sepa-
rate 32-bit instruction and data busses running at full speed
to execute programs and access data from both on-chip and
external memory. A standard set of peripherals are also
CoreConnect™ enabled to offer MicroBlaze designers com-
patibility and reuse.
All IP cores for Virtex-4 FPGAs are found on the Xilinx IP
Center Internet portal presenting the latest intellectual prop-
erty cores and reference designs via Smart Search for
faster access.
Application Notes and Reference Designs
Application notes and reference designs written specifically
for the Virtex-4 family are available on the Xilinx web site at:
http://www.xilinx.com/virtex4
DS112 (v1.1) September 10, 2004
www.xilinx.com
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Advance Product Specification