XC4VLX15 Datasheet, PDF (6/10 Pages) Xilinx, Inc – High-performance logic applications solution

Virtex-4 Family Overview
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XtremeDSP Slices
The XtremeDSP slices contain a dedicated 18 x 18-bit 2’s
complement signed multiplier, adder logic, and a 48-bit
accumulator. Each multiplier or accumulator can be used
independently. These blocks are designed to implement
extremely efficient and high-speed DSP applications.
The block DSP feature in Virtex-4 devices are further dis-
cussed in XtremeDSP Design Considerations.
Global Clocking
The DCM and global-clock multiplexer buffers provide a
complete solution for designing high-speed clock networks.
Up to twenty DCM blocks are available. To generate
deskewed internal or external clocks, each DCM can be
used to eliminate clock distribution delay. The DCM also
provides 90°, 180°, and 270° phase-shifted versions of the
output clocks. Fine-grained phase shifting offers higher res-
olution phase adjustment with fraction of the clock period
increments. Flexible frequency synthesis provides a clock
output frequency equal to a fractional or integer multiple of
the input clock frequency.
Virtex-4 devices have 32 global-clock MUX buffers. The
clock tree is designed to be differential. Differential clocking
helps reduce jitter and duty cycle distortion.
Routing Resources
All components in Virtex-4 devices use the same intercon-
nect scheme and the same access to the global routing
matrix. Timing models are shared, greatly improving the
predictability of the performance for high-speed designs.
System Monitor
The basic building block of any digital system monitoring
function is an Analog-to-Digital Converter (ADC). The ADC
is capable of capturing 10-bits of information at 200 Ksps.
Additional circuitry is used to monitor various parameters.
System Monitor features include on-chip/off-chip supply
voltage and temperature monitoring, and supply voltage
peak / sag capture. A stand-alone ADC is available in the
larger devices.
The Virtex-4 System Monitor is covered in depth in the
Virtex-4 User Guide.
Boundary Scan
Boundary-scan instructions and associated data registers
support a standard methodology for accessing and config-
uring Virtex-4 devices, complying with IEEE standards
1149.1 and 1532.
Configuration
Virtex-4 devices are configured by loading the bitstream into
internal configuration memory using one of the following
modes:
• Slave-serial mode
• Master-serial mode
• Slave SelectMAP mode
• Master SelectMAP mode
• Boundary-scan mode (IEEE-1532)
Optional 256-bit AES decryption is supported on-chip (with
software bitstream encryption) providing Intellectual Prop-
erty security.
Virtex-4 FX Family
This section briefly describes blocks available only in FX devices.
RocketIO Multi-Gigabit Transceiver
8 - 24 Channels RocketIO Multi-Gigabit Serial Transceivers
(MGTs) capable of running 622 Mb/s - 11.1 Gb/s
• Full Clock and Data Recovery
• 32-bit or 40-bit datapath support
• Optional 8b/10b, 64b/66b, or FPGA-based
encode/decode
• Integrated FIFO/Elastic Buffer
• Support for Channel Bonding
• Embedded 32-bit CRC generation/checking
• Integrated Comma-detect or programmable A1/A2,
A1A1/A2A2 detection
• Programmable pre-emphasis (AKA transmitter
equalization)
• Programmable receiver equalization
• Embedded support for:
- Out of Band (OOB) Signalling: Serial ATA
- Beaconing and Electrical Idle: PCI-Express™
• On-chip bypassable AC coupling for receiver
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DS112 (v1.1) September 10, 2004
Advance Product Specification