XC4VLX15 Datasheet, PDF (1/10 Pages) Xilinx, Inc – High-performance logic applications solution

Virtex-4 User Guide
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Virtex-4 Family Overview
DS112 (v1.1) September 10, 2004
0 0 _{Advance Product Specification}
General Description
The Virtex-4™ Family is the newest generation FPGA from Xilinx. The innovative Advanced Silicon Modular Block or
ASMBL™ column-based architecture is unique in the programmable logic industry. Virtex-4 FPGAs contain three families
(platforms): LX, FX, and SX. Choice and feature combinations are offered for all complex applications. A wide array of
hard-IP core blocks complete the system solution. These cores include the PowerPC™ processors (with a new APU
interface), Tri-Mode Ethernet MACs, 622 Mb/s to 11.1 Gb/s serial transceivers, voltage/temperature system monitor blocks,
dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4
building blocks are an enhancement of those found in the popular Virtex-based product families: Virtex, Virtex-E, Virtex-II,
Virtex-II Pro, and Virtex-II Pro X, allowing upward compatibility of existing designs. Virtex-4 devices are produced on a
state-of-the-art 90-nm copper process, using 300 mm (12 inch) wafer technology. Combining a wide variety of flexible
features, the Virtex-4 family enhances programmable logic design capabilities and is a powerful alternative to ASIC
technology.
Summary of Virtex-4 Features
• Three families LX/SX/FX
- Virtex-4 LX: High-performance logic applications solution
- Virtex-4 FX: High-performance, full-featured solution for
embedded platform applications
- Virtex-4 SX: High-performance solution for Digital Signal
Processing (DSP) applications
• Xesium™ Clock Technology
- Digital Clock Manager (DCM) blocks
- Additional Phase-Matched Clock Dividers (PMCD)
- Differential Global Clocks
• XtremeDSP™ Slice
- 18x18, two’s complement, signed Multiplier
- Optional pipeline stages
- Built-In Accumulator (48-bits) & Adder/Subtracter
• Smart RAM Memory Hierarchy
- Distributed RAM
- Dual-Port 18-Kbit RAM blocks
· Optional pipeline stages
· Optional programmable FIFO logic - Automatically
remaps RAM signals as FIFO signals
- High-speed memory interface support: DDR and DDR-2
SDRAM, QDR-II, RLDRAM-II, and FCRAM-II
• SelectIO Technology
- 1.5 to 3.3 V I/O Operation
- Built-In ChipSync™ Source-Synchronous Technology
- Digitally-controlled impedance (DCI) active termination
- Fine grained I/O banking (Configuration in one bank)
• Flexible Logic Resources
• Built-in System Monitor (voltage/temp. measurement)
• 10-bit, 200kSPS A/D Converter (ADC)
• Secure Chip AES Bitstream Encryption
• 90-nm copper CMOS process
• 1.2V core voltage
• Flip-Chip Packaging
• RocketIO™ 622 Mb/s to 11.1 Gb/s Multi-Gigabit
Transceivers (MGT) (FX only)
• IBM PowerPC RISC Processor Core (FX only)
- PowerPC 405 (PPC405) Core
- Auxiliary Processor Unit Interface (User Coprocessor)
• Multiple Tri-Mode Ethernet MACs (FX only)
Table 1: Virtex-4 FPGA Family Members
Device
Configurable Logic Blocks (CLBs)⁽¹⁾
Block RAM
Array Logic
Row x Col Cells
Xtreme
Slices
Max
DSP 18 Kb
Distributed Slices⁽²⁾ Blocks
Max
Block
DCMs
PMCDs
System
Monitors
ADC
Blocks
PowerPC
Processor
Blocks
Ethernet
MACs
RocketIO
Transciever
Blocks
Total
I/O
Banks
Max
User
I/O
RAM (Kb)
RAM (Kb)
XC4VLX15 64 x 24 13,824 6,144
96
32
48
864
4
0
0
0
N/A
N/A
N/A
9 320
XC4VLX25 96 x 28 24,192 10,752
168
48
72
1,296
8
4
1
0
N/A
N/A
N/A
11 448
XC4VLX40 128 x 36 41,472 18,432
288
64
96
1,728
8
4
1
0
N/A
N/A
N/A
13 640
XC4VLX60 128 x 52 59,904 26,624
416
64
160
2,880
8
4
1
0
N/A
N/A
N/A
13 640
XC4VLX80 160 x 56 80,640 35,840
560
80
200 3,600 12
8
1
1
N/A
N/A
N/A
15 768
XC4VLX100 192 x 64 110,592 49,152
768
96
240 4,320 12
8
1
1
N/A
N/A
N/A
17 960
XC4VLX160 192 x 88 152,064 67,584 1056
96
288 5,184 12
8
1
1
N/A
N/A
N/A
17 960
XC4VLX200 192 x 116 200,448 89,088 1392
96
336 6,048 12
8
1
1
N/A
N/A
N/A
17 960
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS112 (v1.1) September 10, 2004
www.xilinx.com
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Advance Product Specification