XC4VLX15 Datasheet, PDF (5/10 Pages) Xilinx, Inc – High-performance logic applications solution

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Virtex-4 Family Overview
Virtex-4 Features
This section briefly describes the features of the Virtex-4 family of FPGAs.
Input/Output Blocks (SelectIO)
IOBs are programmable and can be categorized as follows:
• Programmable single-ended or differential (LVDS)
operation
• Input block with an optional single data rate (SDR) or
double data rate (DDR) register
• Output block with an optional SDR or DDR register
• Bidirectional block
• Per-bit deskew circuitry
• Dedicated I/O and regional clocking resources
• Built in data serializer/deserializer
General purpose I/O in select locations (four per bank) are
designed to be "regional clock capable" I/O by adding spe-
cial hardware connections for I/O in the same locality. These
regional clock inputs are distributed within a limited region
to minimize clock skew between IOBs. Regional I/O clock-
ing supplements the global clocking resources.
Data serializer/deserializer capability is added to every I/O
to support source synchronous interfaces. A serial-to-paral-
lel converter with associated clock divider is included in the
input path, and a parallel-to-serial converter in the output
path.
The IOB registers are either edge-triggered D-type flip-flops An in-depth guide to the Virtex-4 IOB is discussed in the
or level-sensitive latches.
Virtex-4 User Guide.
IOBs support the following single-ended standards:
Configurable Logic Blocks (CLBs)
• LVTTL
• LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
• PCI (33 and 66 MHz)
• PCI-X
• GTL and GTLP
• HSTL 1.5V and 1.8V (Class I, II, III, and IV)
• SSTL 1.8V and 2.5V (Class I and II)
The DCI I/O feature can be configured to provide on-chip
termination for each single-ended I/O standard and some
differential I/O standards.
The IOB elements also support the following differential sig-
naling I/O standards:
• LVDS and Extended LVDS (2.5V only)
• BLVDS (Bus LVDS)
• ULVDS
• Hypertransport™
• Differential HSTL 1.5V and 1.8V (Class II)
• Differential SSTL 1.8V and 2.5V (Class II)
Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.
Per-bit deskew circuitry allows for programmable signal
delay internal to the FPGA. Per-bit deskew flexibly provides
fine-grained increments of delay to carefully produce a
range of signal delays. This is especially useful for synchro-
nizing signal edges in source synchronous interfaces.
A CLB resource is made up of four slices. Each slice is
equivalent and contains:
• Two function generators (F & G)
• Two storage elements
• Arithmetic logic gates
• Large multiplexers
• Fast carry look-ahead chain
• Horizontal cascade chain
The function generators F & G are configurable as 4-input
look-up tables (LUTs). Two slices in a CLB can have their
LUTs configured as 16-bit shift registers, or as 16-bit distrib-
uted RAM. In addition, the two storage elements are either
edge-triggered D-type flip-flops or level sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
The Virtex-4 CLBs are further discussed in the Virtex-4
User Guide.
Block RAM
The block RAM resources are 18 Kb true dual-port RAM
blocks, programmable from 16K x 1 to 512 x 36, in various
depth and width configurations. Each port is totally synchro-
nous and independent, offering three "read-during-write"
modes. Block RAM is cascadable to implement large
embedded storage blocks. Additionally, back-end pipeline
registers, clock control circuitry, built-in FIFO support, and
byte write enable are new features supported in the Virtex-4
FPGA.
The block RAM feature in Virtex-4 devices is further dis-
cussed in the Virtex-4 User Guide.
DS112 (v1.1) September 10, 2004
www.xilinx.com
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Advance Product Specification