XC4VLX15 Datasheet, PDF (3/10 Pages) Xilinx, Inc – High-performance logic applications solution

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Virtex-4 Family Overview
SelectIO Technology
• Up to 960 user I/Os
• Wide selections of I/O standards from 1.5V to 3.3V
• Extremely high-performance
- 600 Mb/s HSTL & SSTL (on all single-ended I/O)
- 1 Gb/s LVDS (on all differential I/O pairs)
• True differential termination
• Selected low-capacitance I/Os for improved signal
integrity
• Same edge capture at input and output I/Os
• Memory interface support for DDR and DDR-2
SDRAM, QDR-II, RLDRAM-II, and FCRAM-II
ChipSync Technology
• Integrated with SelectIO technology to simplify
source-synchronous interfaces
• Per-bit deskew capability built in all I/O blocks (variable
input delay line)
• Dedicated I/O and regional clocking resources (pin and
trees)
• Built in data serializer/deserializer logic in all I/O and
clock dividers
• Memory/Networking/Telecommunication interfaces up
to 1 Gb/s+
Digitally Controlled Impedance (DCI)
Active I/O Termination
• Optional series or parallel termination
• Temperature compensation
System Monitor
• On-chip or off-chip temperature sensing capability
• On-chip or off-chip voltage monitoring capability
• Peak detect and alarm features
A/D Converter Blocks
• Supplemental A/D converter block in selected devices
• 10-bit / 200 kilo samples per second (kSPS or KHz)
• Dedicated analog I/O pins
Configuration
• 256-bit AES bitstream decryption provides intellectual
property (IP) security
• Improved bitstream error detection/correction capability
• Fast SelectMAP configuration
• JTAG support
• Readback capability
90 nm Copper CMOS Process
1.2V Core Voltage
System Blocks Specific to the FX Family
RocketIO Multi-Gigabit Transceiver (MGT)
• Full-duplex serial transceiver (MGT) capable of
622 Mb/s to 11.1 Gb/s baud rates
• 8b/10b, 64b/66b, user-defined FPGA logic, or no data
encoding
• Channel bonding support
• CRC generation and checking
• Programmable pre-emphasis or pre-equalization for
the transmitter
• Programmable continuous time equalization for the
receiver
• Programmable discrete feedback equalization for the
receiver
• On-chip AC coupled receiver
• Receiver signal detect and loss of signal indicator
• Transmit driver sleep mode
• User dynamic reconfiguration using secondary
configuration bus
PowerPC 405 RISC Core
• Embedded PowerPC 405 (PPC405) core
- Up to 450 MHz operation
- Five-stage data path pipeline
- 16 KB instruction cache
- 16 KB data cache
- Enhanced instruction and data on-chip memory
(OCM) controllers
- Additional frequency ratio options between
PPC405 and Processor Local Bus
• Auxiliary Processor Unit (APU) Interface for direct
connection from PPC405 to coprocessors in fabric
- APU can run at different clock rates
- Supports autonomous instructions: no pipeline
stalls
- 32-bit instruction and 64-bit data
- 4-cycle cache line transfer
DS112 (v1.1) September 10, 2004
www.xilinx.com
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Advance Product Specification