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XC2C128-7VQG100I Datasheet, PDF (7/18 Pages) Xilinx, Inc – Optimized for 1.8V systems
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XC2C128 CoolRunner-II CPLD
AC Electrical Characteristics Over Recommended Operating Conditions
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Symbol
Parameter
Min. Max. Min. Max. Units
TPD1
Propagation delay single p-term
-
5.7
-
7.0 ns
TPD2
Propagation delay OR array
-
6.0
-
7.5 ns
TSUD
Direct input register set-up time
3.6
-
4.6
-
ns
TSU1
Setup time fast (single p-term)
2.4
-
3.0
-
ns
TSU2
Setup time (OR array)
2.7
-
3.5
-
ns
THD
Direct input register hold time
0.0
-
0.0
-
ns
TH
Hold time (Or array or p-term)
0.0
-
0.0
-
ns
TCO
FTOGGLE(1)
FSYSTEM1(2)
Clock to output
Internal toggle rate
Maximum system frequency
-
4.2
-
5.4 ns
-
450
- 300 MHz
-
244
- 152 MHz
FSYSTEM2(2)
FEXT1(3)
FEXT2(3)
Maximum system frequency
Maximum external frequency
Maximum external frequency
-
227
- 141 MHz
-
152
- 119 MHz
-
145
- 112 MHz
TPSUD
Direct input register p-term clock setup time
2.5
-
3.1
-
ns
TPSU1
P-term clock setup time (single p-term)
1.3
-
1.5
-
ns
TPSU2
P-term clock setup time (OR array)
1.6
-
2.0
-
ns
TPHD
Direct input register p-term clock hold time
0.2
-
0.2
-
ns
TPH
P-term clock hold
0.7
-
1.0
-
ns
TPCO
P-term clock to output
-
5.9
-
7.3 ns
TOE/TOD
Global OE to output enable/disable
-
5.9
-
7.5 ns
TPOE/TPOD
P-term OE to output enable/disable
-
7.0
-
8.5 ns
TMOE/TMOD Macrocell driven OE to output enable/disable
-
7.7
-
9.9 ns
TPAO
P-term set/reset to output valid
-
6.6
-
8.1 ns
TAO
Global set/reset to output valid
-
5.0
-
7.6 ns
TSUEC
Register clock enable setup time
3.1
-
3.5
-
ns
THEC
Register clock enable hold time
0.0
-
0.0
-
ns
TCW
Global clock pulse width High or Low
1.1
-
1.6
-
ns
TAPRPW
Asynchronous preset/reset pulse width (High or Low)
6.0
-
7.5
-
ns
TPCW
P-term pulse width High or Low
6.0
-
7.5
-
ns
TDGSU
Set-up before DataGATE latch assertion
0.0
-
0.0
-
ns
TDGH
Hold to DataGATE latch assertion
4.0
-
6.0
-
ns
TDGR
DataGATE recovery to new data
-
8.2
-
9.0 ns
TDGW
DataGATE low pulse width
3.0
-
4.0
-
ns
TCDRSU
CDRST setup time before falling edge GCLK2
1.3
-
2.0
-
ns
TCDRH
TCONFIG(4)
Hold time CDRST after falling edge GCLK2
Configuration time
0.0
-
0.0
-
ns
-
350
- 350 us
Notes:
1. FTOGGLE is the maximum clock frequency to which a T flip-flop can reliably toggle (see the CoolRunner-II family data sheet).
2. FSYSTEM1 is the internal operating frequency for a device with 16-bit resetable binary counter through one p-term per macrocell while
FSYSTEM2 is through the OR array (one counter per function block).
3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array.
4. Typical configuration current during TCONFIG is 10 mA.
DS093 (v3.2) March 8, 2007
www.xilinx.com
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Product Specification
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