XC2C128-7VQG100I Datasheet, PDF (10/18 Pages) Xilinx, Inc – Optimized for 1.8V systems

XC2C128 CoolRunner-II CPLD
R
Typical I/V Output Curves
The I/V curve illustrates the nominal amount of current that an I/O can source/sink at different voltage levels.
60
3.3V
50
40
1.8V
2.5V
30
Iol
20
1.5V
10
0
0
.5
1.0
1.5
2.0
VO (Output Volts)
2.5
3.0
3.5
XC128_IV_all_050703
Figure 4: Typical I/V Curves for XC2C128
11
Pin Descriptions
Function Macro-
Block
cell VQ100 CP132 TQ144
1
1
13
G1
17
1
2
-
F1
16
1
3
12
F2
15
1
4
11
F3
14
1
5
10
E1
13
1
6
9
E2
12
1
7
-
-
-
1
8
-
-
-
1
9
-
-
-
1
10
-
-
-
1
11
8
E3
11
1
12
7
D1 10
1
13
6
D2
9
1
14
-
C1
7
1(GTS1)
15
4
C2
6
1(GTS0)
16
3
C3
5
I/O
Bank
2
2
2
2
2
2
-
-
-
-
2
2
2
2
2
2
Pin Descriptions (Continued)
Function Macro-
I/O
Block
cell VQ100 CP132 TQ144 Bank
2
1
-
G2
19
1
2
2
14
G3
21
1
2
3
15
H1
22
1
2
4
16
H2
23
1
2
5
17
H3
24
1
2
6
18
J1
25
1
2
7
-
-
-
-
2
8
-
-
-
-
2
9
-
-
-
-
2
10
-
-
-
-
2
11
19
J2
26
1
2
12
-
K1
28
1
2(GCK0)
13
22
K3
30
1
2(GCK1)
14
23
L2
32
1
2(CDRST) 15
24
M2
35
1
2(GCK2)
16
27
N2
38
1
10
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DS093 (v3.2) March 8, 2007
Product Specification