XC2C128-7VQG100I Datasheet, PDF (12/18 Pages) Xilinx, Inc – Optimized for 1.8V systems

XC2C128 CoolRunner-II CPLD
R
Pin Descriptions (Continued)
Function Macro-
I/O
Block
cell VQ100 CP132 TQ144 Bank
7
1
77 C12 112
2
7
2
78 B12 113
2
7
3
-
A12 115
2
7
4
79 C11 116
2
7
5
80 B11 117
2
7
6
81 A11 118
2
7
7
-
C10 119
2
7
8
-
-
-
-
7
9
-
-
-
-
7
10
-
-
-
-
7
11
82 A10 120
2
7
12
-
C9 121
2
7
13
85
A8 124
2
7
14
86
B8 125
2
7
15
87
C8 126
2
7
16
89
B7 128
2
Pin Descriptions (Continued)
Function Macro-
I/O
Block
cell VQ100 CP132 TQ144 Bank
8
1
-
N14 77
1
8
2
53 N13 76
1
8
3
52 P14 74
1
8
4
50 P12 71
1
8
5
-
M11 70
1
8
6
49 N11 69
1
8
7
-
-
-
-
8
8
-
-
-
-
8
9
-
-
-
-
8
10
-
-
-
-
8
11
-
P11 68
1
8
12
46 P10 64
1
8
13
44
P9
61
1
8
14
43
M8
60
1
8
15
42
N8
59
1
8
16
41
P8
58
1
Notes:
1. GTS = global output enable, GSR = global reset/set, GCK =
global clock, CDRST = clock divide reset, DGE = DataGATE
enable.
2. GCK, GSR, and GTS pins can also be used for general
purpose I/O.
12
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DS093 (v3.2) March 8, 2007
Product Specification