XC2C128-7VQG100I Datasheet, PDF (2/18 Pages) Xilinx, Inc – Optimized for 1.8V systems

XC2C128 CoolRunner-II CPLD
R
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II 128
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
The CoolRunner-II 128 macrocell CPLD is I/O compatible
with various JEDEC I/O standards (see Table 1). This
device is also 1.5V I/O compatible with the use of
Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
RealDigital technology, a design technique that makes use
of CMOS technology in both the fabrication and design
methodology. RealDigital technology employs a cascade of
CMOS gates to implement sum of products instead of tradi-
tional sense amplifier methodology. Due to this technology,
Xilinx CoolRunner-II CPLDs achieve both high-perfor-
mance and low power operation.
Supported I/O Standards
The CoolRunner-II 128 macrocell features LVCMOS,
LVTTL, SSTL and HSTL I/O implementations. See Table 1
for I/O standard voltages. The LVTTL I/O standard is a gen-
eral purpose EIA/JEDEC standard for 3.3V applications that
use an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
Both HSTL and SSTL make use of a V_REF pin for JEDEC
compliance. CoolRunner-II CPLDs are also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C128⁽¹⁾
IOSTANDARD Output
Attribute
V_CCIO
LVTTL
3.3
Input
V_CCIO
3.3
Input
V_REF
N/A
Board
Termination
Voltage V_TT
N/A
LVCMOS33
3.3
3.3 N/A
N/A
LVCMOS25
2.5
2.5 N/A
N/A
LVCMOS18
1.8
1.8 N/A
N/A
LVCMOS15⁽²⁾ 1.5
1.5 N/A
N/A
HSTL_1
1.5
1.5 0.75
0.75
SSTL2_1
2.5
2.5 1.25
1.25
SSTL3_1
3.3
3.3 1.5
1.5
(1) For information on assigning Vref pins, see XAPP399
(2) LVCMOS15 requires use of Schmitt-trigger inputs.
40
20
0
0
50
100
150
200
250
Frequency (MHz)
DS093_041905
Figure 1: I_CC vs Frequency
Table 2: I_CC vs Frequency (LVCMOS 1.8V T_A = 25°C)⁽¹⁾
Frequency (MHz)
0
25
50
75 100 150 175
Typical I_CC (mA)
0.019 3.97 7.95 11.92 15.89 23.83
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
27.80
200
31.93
225
35.73
250
39.70
2
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DS093 (v3.2) March 8, 2007
Product Specification