XA3S1500-4FGG456I Datasheet, PDF (7/8 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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Introduction and Ordering Information
Pb-Free Packaging
For additional information on Pb-free packaging, see XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free
Packages.
Example: XA3S50 -4 PQ G 208 Q
Device Type
Speed Grade
Package Type
Temperature Range:
Q-Grade = Automotive Extended (T_J = –40°C to +125°C)
I-Grade = Automotive Industrial (T_J = –40°C to +100°C)
Number of Pins
Pb-free
DS314-1_03_100808
Table 6: Package Types and Number of Pins
Device
Speed Grade
Package Type / Number of Pins
XA3S50
-4
Standard
Performance
VQG100 100-pin Very Thin Quad Flat Pack (VQFP)
XA3S200
TQG144 144-pin Thin Quad Flat Pack (TQFP)
XA3S400
PQG208 208-pin Plastic Quad Flat Pack (PQFP)
XA3S1000
FTG256
256-ball Fine-Pitch Thin Ball Grid Array
(FTBGA)
XA3S1500
FGG456 456-ball Fine-Pitch Ball Grid Array (FBGA)
FGG676 676-ball Fine-Pitch Ball Grid Array (FBGA)
Temperature Range (T_J)
I I-Grade (–40°C to +100°C)
Q Q-Grade (–40°C to +125°C)
Additional Resources
• DS099, Spartan-3 FPGA Family Data Sheet
• UG331, Spartan-3 Generation FPGA User Guide
• UG332, Spartan-3 Generation Configuration User Guide
Revision History
The following table shows the revision history for this document:
Date
10/18/04
12/20/04
10/27/06
11/28/06
11/12/07
01/25/08
06/18/09
Version
1.0
1.1
1.2
1.2.1
1.2.2
1.2.3
1.3
Description
Initial Xilinx release.
Multiple text edits throughout.
Updated IO standards (Table 2), and link to Spartan-3 Data Sheet, added XA3S1500, TQG144, FGG676,
Table 4, and Table 5.
Changed order of explanations in Table 6 for TQG144 and PQG208.
Changed all values for the Block RAM (bits) column and two values for the XA3S1000 row in Table 1.
Changed XA3S1500 Q-Grade Maximum in Table 5.
Added UG331 and UG332 to "Additional Resources" section.
DS314 (v1.3) June 18, 2009
www.xilinx.com
Product Specification
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