XA3S1500-4FGG456I Datasheet, PDF (1/8 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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DS314 (v1.3) June 18, 2009
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XA Spartan-3 Automotive FPGA Family:
Introduction and Ordering Information
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Product Specification
Summary
The Xilinx® Automotive (XA) Spartan®-3 family of Field-Programmable Gate Arrays meets the needs of high-volume,
cost-sensitive automotive electronic applications. The five-member family offers densities ranging from 50,000 to 1.5 million
system gates, as shown in Table 1.
Introduction
Features
XA devices are available in both extended-temperature
Q-grade (–40°C to +125°C T_J) and I-grade (–40°C to
+100°C T_J) and are qualified to the industry-recognized
AEC-Q100 standard.
The XA Spartan-3 family builds on the success of the earlier
XA Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. These Spartan-3
enhancements, combined with advanced process
technology, deliver more functionality and bandwidth per
dollar than was previously possible, setting new standards
in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of advanced automotive
electronics modules and systems ranging from the latest
driver assistance and infotainment systems to instrument
clusters and gateways.
• AEC-Q100 device qualification and full PPAP
documentation support available in both extended
temperature Q-grade and I-grade
• Guaranteed to meet full electrical specification over the
T_J = –40°C to +125°C temperature range
• Revolutionary 90-nanometer process technology
• Low cost, high-performance logic solution for
high-volume, automotive applications
♦ Three power rails: for core (1.2V), I/Os (1.2V to
3.3V), and auxiliary purposes (2.5V)
• SelectIO™ interface signaling
♦ Up to 487 I/O pins
♦ 622 Mb/s data transfer rate per I/O
♦ Eighteen single-ended signal standards
♦ Eight differential signal standards including LVDS
♦ Termination by Digitally Controlled Impedance
The Spartan-3 family is a flexible alternative to ASICs,
ASSPs, and microcontrollers. FPGAs avoid the high initial
NREs, the lengthy development cycles, and problems with
obsolescence. Also, FPGA programmability permits design
upgrades in the field with no hardware replacement
necessary.
♦ Signal swing ranging from 1.14V to 3.45V
♦ Double Data Rate (DDR) support
• Logic resources
♦ Abundant logic cells with shift register capability
♦ Wide multiplexers
Table 1: Summary of Spartan-3 FPGA Attributes
Device
XA3S50
XA3S200
XA3S400
XA3S1000
XA3S1500
System
Gates
50K
200K
400K
1M
1.5M
Logic
Cells
1,728
4,320
8,064
17,280
29,952
CLB Array
(One CLB = Four Slices)
Rows Columns Total CLBs
16
12
192
24
20
480
32
28
896
48
40
1,920
64
52
3,328
Distributed
RAM (bits¹)
12K
30K
56K
120K
208K
Block RAM
(bits¹)
72K
216K
288K
432K
576K
Dedicated
Multipliers
4
12
16
24
32
DCMs
2
4
4
4
4
Maximum
User I/O
124
173
264
333
487
Maximum
Differential
I/O Pairs
56
76
116
149
221
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
© 2004–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium in the U.S. and other jurisdictions. All other trademarks are the property of their
respective owners.
DS314 (v1.3) June 18, 2009
www.xilinx.com
Product Specification
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