XA3S1500-4FGG456I Datasheet, PDF (3/8 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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Introduction and Ordering Information
Notes:
1. The XA3S50 has only the block RAM column on the far left.
DS314-1_01_100808
Figure 1: Spartan-3 Family Architecture
Configuration
Spartan-3 FPGAs are programmed by loading configuration
data into robust static memory cells that collectively control
all functional elements and routing resources. Before
powering on the FPGA, configuration data is stored
externally in a PROM or some other nonvolatile medium
either on or off the board. After applying power, the
configuration data is written to the FPGA using any of five
different modes: Master Parallel, Slave Parallel, Master
Serial, Slave Serial and Boundary Scan (JTAG). The Master
and Slave Parallel modes use an 8-bit-wide SelectMAP
port.
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I/O Capabilities
The SelectIO feature of Spartan-3 devices supports 18
single-ended standards and eight differential standards as
listed in Table 2. Many standards support the DCI feature,
which uses integrated terminations to eliminate unwanted
signal reflections. Table 3 shows the number of user I/Os as
well as the number of differential I/O pairs available for each
device/package combination.
DS314 (v1.3) June 18, 2009
www.xilinx.com
Product Specification
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